rhee - DESIGN OF HIGH-PERFORMANCE CMOS CHARGE PUMPS IN...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
DESIGN OF HIGH-PERFORMANCE CMOS CHARGE PUMPS IN PHASE-LOCKED LOOPS Woogeun Rhee Conexant Systems, Inc.* Newport Beach, California 92660, USA *Formerly, Rockwell Semiconductor Systems, Inc. ABSTRACT Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump by the leakage current, the mismatch, and the delay offset in the P/FD are quantita- tively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their perfor- mances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result. 1. INTRODUCTION A charge pump is widely used in modem phase-locked loops (PLL) for a low-cost IC solution as shown in Fig. 1. Having the neutral state, the ideal charge pump combined with the P/FD provides the infinite dc gain with passive filters, which results in the unbounded pull-in range for 2nd-order and high-order PLLs if not limited by VCO input range [ 11. As long as the P/FD and the charge pump are ideal, the zero static phase error is achieved. In other words, the type-2 PLL is possible with the passive filter when the charge pump is employed. The charge pump, however, shows non-ideal behavior when imple- mented in the circuit and its practical issues need to be considered in the design of the PLL. In this work, design considerations of the CMOS charge pumps are addressed and various architectures are investigated. 2. DESIGN CONSIDERATIONS One of the practical design issues in PLLs is the unbalanced large- signal operation related with the charge pump that transforms the timing information to analogue quantity in voltage to control the VCO. When the PLL is used as a digital clock generator for high- speed I/O interfaces, minimizing the clock skew between the internal clock and the external clock is important to get the maximum data bandwidth and the clock skew is mainly determined by the non-ideal charge pump. In frequency synthesis, the charge pump is the domi- nant block that determines the level of the unwanted FM modulation causing the reference spur. Therefore, the non-ideal effect of the charge pump should be carefully considered. 2.1. Leakage Current One of the issues in the charge pump design is the leakage current which might be caused by the charge pump itself, by the on-chip var- actor, or by any leakage in the board. The leakage current as high as 1 nA can be easily present in sub-micron CMOS. The phase offset due to the leakage current is usually negligible but the reference spur by the leakage current is possibly substantial in frequency synthesizers. Q ldNl Locked without offset Locked wilh offset 1 4 Figure 1. Charge-pump PLL : (a) functional block diagram, and (b) timing diagram with offset and without offset. The phase offset,
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 4

rhee - DESIGN OF HIGH-PERFORMANCE CMOS CHARGE PUMPS IN...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online