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ECE265APaper17

ECE265APaper17 - 1 A Capacitance-Compensation Technique for...

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1 A Capacitance-Compensation Technique for Improved Linearity in CMOS Class-AB Power Amplifiers Chengzhou Wang, Student Member, IEEE , Mani Vaidyanathan, Member, IEEE , and Lawrence E. Larson, Fellow, IEEE This work was supported by the UCSD Center for Wireless Communications, its member companies, and the State of Cali- fornia on a UC Discovery Grant. The authors are with the Center for Wireless Communications, Department of Electrical and Computer Engineering, Univer- sity of California, San Diego, La Jolla, CA 92093-0407. Tel. (858) 534-8987. Fax (858) 822-3425.
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2 Abstract A nonlinear, capacitance-compensation technique is developed to help improve the linearity of CMOS class- AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0 . 5 μ m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized power amplifier meets 3GPP- WCDMA ACP requirements at the designed output power of 24 dBm, with a power-added efficiency of 29 % and a gain of 23.9 dB. Keywords CMOS, radio-frequency (RF) circuits, class-AB power amplifiers, WCDMA, linearity, intermodulation distor- tion, adjacent-channel-power-ratio (ACPR), Volterra series. I. I NTRODUCTION Presently, there is widespread interest in pursuing a single-chip, handheld, wireless transceiver implemented in complementary, metal-oxide-semiconductor (CMOS) technology. A key com- ponent of such a system would be the power amplifier (PA), and several workers have recently described implementations of CMOS PAs. However, most of these designs, such as those de- scribed in [1]–[4], were intended for constant-envelope modulation schemes, and are hence intrinsically very nonlinear. For non-constant-envelope modulation schemes, nonlinearity can cause severe regrowth in the spectral sidebands and an increase in the transmitted error-vector magnitude. In such cases, stringent requirements are placed on amplifier linearity. At the same time, to prolong battery life, the power amplifier must also operate at reasonable levels of effi- ciency. To meet the simultaneous requirements of high linearity and reasonable efficiency, power amplifiers in non-constant-envelope systems are often operated in a class-AB mode; the linear- ity can be superior to that in class-B or higher operation and the efficiency is superior to that in class-A operation. Of particular importance is the nonlinearity of the class-AB amplifier; while more linear than a class-B or higher amplifier, the intrinsic linearity obtained in class-AB oper- ation is often still insufficient to meet required specifications. While many external linearization
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3 techniques are known [5, Ch. 9], they are complex and inconvenient for handset applications,
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