s08-final-solution

S08-final-solution - ECE 108 Final Exam Friday June 13 Spring 2008 You are reminded that academic dishonesty will NOT be tolerated You have 3 hours

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ECE 108 Final Exam Friday, June 13 Spring 2008 You are reminded that academic dishonesty will NOT be tolerated. You have 3 hours to complete the exam. You may refer to 1 sheet of your own hand-written notes but no other reference material. You may also use a calculator. Question Your points Out of 1 10 2 10 3 10 4 10 5 10 6 10 Total 60 Name Solution Student ID Signature Extra credit: Describe how the legend of “Friday the Thirteenth” came about.
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The circuit below is a static random access memory (SRAM) cell and part of its control. During a write operation, write signal becomes high; if 1 needs to be written into the cell, bit also becomes high; if 0 needs to be written in, bit becomes high instead. Before a read operation, out and out are first precharged, then both bit and bit become high, causing the contents of node 1 and node 2 to be read out to out and out . Assume that V DD = 2 . 5 V ; k 0 n = 120 μA/V 2 ; k 0 p = - 30 μA/V 2 ; V tn = 0 . 4 V and V DSATN = 0 . 5 V for all nMOS, and V tp = - 0 . 4 V and V DSATP = - 1 V for all pMOS transistors; L n = L p = 1 ; the width of M 1 , M 2 , M 3 , and M 4 is W n ; the width of the pMOS precharge transistors is W p ; the widths of the nMOS and pMOS transistors in INV 1 and INV 2 are W INVn and W INVp respectively; V OL = k 0 p k 0 n W p W n V DSATP when nMOS in triode and pMOS in saturation if V tn = | V tp | . V DD V DD bit bit out out prech prech write write Sense Amplifer Y Y M 1 M 2 M 3 M 4 INV 1 INV 2 C I C I C O C O (a) (5 points) Determine the relative sizing of the transistors that allows a new data bit is written into the cell. Justify your answer. Consider the case in which 1 is written into the cell. The nMOS stack (consisting of M 2 and M 4 ) must be able to overpower the pMOS transistor (from INV 2 ) to bring the voltage level at node x (see below) down to less than V tn = 0 . 4 V . When V x < 0 . 4 V , both M 2 and M 4 are in triode but the pMOS of INV 2 is in saturation. Thus V x = k 0 p k 0 n W p W n , effective V DSATP . Note that the effective width of the nMOS stack = W n / 2 . 2
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This note was uploaded on 04/03/2011 for the course ECE 108 taught by Professor Kennethy.yun during the Spring '08 term at UCSD.

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S08-final-solution - ECE 108 Final Exam Friday June 13 Spring 2008 You are reminded that academic dishonesty will NOT be tolerated You have 3 hours

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