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Unformatted text preview: NOR implementation than a NAND NAND implementation F1 =AB+A’CD+C’D F2=A’B+AB F3=C(AB+DE) F4= D(CE+A’) How many rows and colums are needed If the unit cell area is 1um2 calculate the area of your PLA Problem 4: A CMOS inverter is used to drive a wire capacitance of CL=15fF. The sum of the gate and drain capacitances of the NMOS device is Cn=5fF . The transconductance parameter of the PMOS is 25uA/V2and for NMOS is 100A/V2. Using VDD = 3V, calculate the W/L ratios of the PMOS and NMOS transistors to minimize propagation delay. What is the propagation delay ? a = ( W/L) p /(W/L) n Problem 5: A pseudo NMOS inverter is used to drive a resistance of 1kOhm. The threshold voltage of the transistors are Vt=+/0.25V. Using VDD = 3V, calculate the the transconductance parameter of the PMOS transistor to ensure a VOH of2.75V and transconductance parameter of the NMOS transistor to achieve VOL of 0.25V?...
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This note was uploaded on 04/03/2011 for the course ECE 108 taught by Professor Kennethy.yun during the Spring '08 term at UCSD.
 Spring '08
 KENNETHY.YUN

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