F09ECE108mixedproblems4final - ECE108 Additional Problems...

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ECE108 Additional Problems for Finals 2003 Dynamic Circuit Design In a DRAM circuit the leakage current per storage cell is measured to be 1nA. Assuming that the storage cell capacitance Cs = 10fF, that the voltage across the storage capacitor is allowed to discharge or charge by only 100mV, and that the sense amplifier can perform a sense and refresh operation every 100ns, calculate the maximum number of storage cells that can be refreshed by this sense amplifier. Pseudo NMOS In the CMOS circuit shown in figure 1, V i is first kept low. a) Estimate V o when the gate of the PMOS transistor is connected to ground. b) Estimate V o when the gate of the PMOS transistor is connected to the 2.5V. Vdd=5V Vo Vi Vg Vtp=-1V Vtn=1V Figure 1 Figure 2: Buffer Design Specifically using relevant equations for the saturated current and capacitance show how the average delay t p =C L V/I av and power dissipation P av = C L V 2 /t p of a long channel MOSFET inverter is scaled when voltages and geometrical dimensions are scaled down (Full scaling). (Hint: C ox ~1/t ox ; C L ~ C ox WL) The minimum size inverter input capacitance is given as 10fF, and t p0 =1ns.This inverter needs to drive the address row (ROW ACCESS) of a ROM circuit that exhibits a parasitic capacitance of 640fF. Design a suitable buffer circuit (provide u) such that the overall propagation delay of the row access driver does not exceed 20ns. Logic synthesis and transistor sizing:
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This note was uploaded on 04/03/2011 for the course ECE 108 taught by Professor Kennethy.yun during the Spring '08 term at UCSD.

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F09ECE108mixedproblems4final - ECE108 Additional Problems...

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