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Unformatted text preview: Solution of ECE65 Final (Fall 2009) Notes: 1. For each problem, 20% of points is for the “correct” final answer. 2. Messy, incoherent papers lose point! Explain what you are doing! 3. Use the following information only in designing circuits: NPN Si transistors have β = 200, β min = 100, r π = 3 kΩ, and r o = 100 kΩ. In circuit design, use 5% tolarence commercial resistor and capacitor values of 1, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2, 2.2, 2.4, 2.7, 3., 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1 ( × 10 n where n is an integer). You can also use 5 mH inductors. Problem 1. Find I in the circuit below with a Si diode. (8pt) V 2 1k 5V 9V 1k 1k 1k I V 1 V 2 v D 1k 5V 9V 1k 1k 1k + I + V 1 V 2 I 1 I 2 1k 5V 9V 1k 1k 1k 0.7 V I Diode OFF Diode ON Case 1: Assume the diode is OFF ( i D = 0 , v D < v γ = 0 . 7 V). Replacing the diode with its circuit model (open circuit), we arrive at the circuit above. By voltage divider formula, we get V 1 = 5 × (1 k ) / (1 k + 1 k ) = 2 . 5 V, and V 2 = 9 × (1 k ) / (1 k + 1 k ) = 4 . 5 V. Then v D = V 2 − V 1 = 4 . 5 − 2 . 5 = 2 > . 7 = V γ . Thus, the diode OFF assumption is incorrect. Case 2: Assume the diode is ON ( i D > , v D = V γ = 0 . 7 V). Replacing the diode with its circuit model (a voltage source), we arrive at the circuit above. Using the nodevoltage method, we note that V 2 = V 1 +0 . 7 and the combination of nodes V 1 and V 2 is a supernode: Supernode V 1 & V 2 V 2 − 9 1 , 000 + V 2 − 1 , 000 + V 1 − 5 1 , 000 + V 1 − 1 , 000 = 0 V 2 − 9 + V 2 + V 1 − 5 + V 1 = 0 2( V 1 + 0 . 7) + 2 V 1 − 14 = 0 → V 1 = 3 . 15 V We use KCL to find I : I = I 2 − I 1 = V 1 − 1 , 000 − 5 − V 1 1 , 000 = 2 V 1 − 5 1 , 000 = 1 . 3 mA Note that since i D = I > 0, the assumption of diode ON is justified. Solution of ECE65 Final (Fall 2009) 1 Method 2: + + 2.5 V 4.5 V 500 500 I Replacing both ladder resistors with their Thevenin equivalents, we arrive at the simple circuit shown. As sume the diode is ON ( i D > , v D = V γ = 0 . 7 V. Then, KVL: − 4 . 5 + 500 I + v D + 500 I + 2 . 5 = 0 I = 4 . 5 − 2 . 5 − . 7 1 , 000 = 1 . 3 mA Since i D = I > 0, the assumption of diode ON is justified....
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This note was uploaded on 04/03/2011 for the course ECE 65 taught by Professor Coles during the Spring '08 term at UCSD.
 Spring '08
 COLES
 Transistor

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