midterm_bonus_solution

midterm_bonus_solution - Problem 7 Cache mapping...

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Problem 7 – Cache mapping schemes (BONUS POINTS) A byte addressable computer has 20-bit memory address space (i.e. 20-bit addresses). The processor has a cache capable of storing 512 words with a block size of 32 words. (Assume word is 2 bytes long as in 68K ISA) a. Assuming the cache uses direct-mapping, how many bits are there in each of the TAG, BLOCK INDEX, and WORD INDEX fields of the address. Show your calculations. Word is 2 bytes: 1 bit to select the byte (A0) Block is 32 words: 5 bits to select the word inside a block (A5-A1) Cache is 512 words, direct-mapped: # of blocks in cache = Cache size (in words) / Block size (in words) = 512 words/32 words/block = 16 blocks Therefore, 4 bits are required to select the block (A9-A6) The rest of the 20-bits is the TAG: 10 bits (A19-A10) TAG (10-bits) BLOCK (4-bits) WORD (5-bits) BYTE (1-bit) A19-A10 A9-A6 A5-A1 A0 b. Assuming the cache uses an 2-way set-associative mapping, how many bits are there in each of the TAG, SET INDEX and WORD INDEX fields of the address. Show your calculations.
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This note was uploaded on 04/03/2011 for the course EE 357 taught by Professor Mayeda during the Spring '08 term at USC.

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midterm_bonus_solution - Problem 7 Cache mapping...

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