EE357Unit10b_Interrupts

EE357Unit10b_Interrupts - Coldfire M68K Interrupts EE 357...

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1 © Mark Redekopp, Al rights reserved EE 357 Unit 10b Interrupts Timers © Mark Redekopp, Al rights reserved Coldfire / M68K Interrupts • Coldfire interrupt architecture is based on original M68K • 3-bit input (IPL[2:0]) indicating interrupt requests/priorities – 000 = No interrupt – 001-111 = Device 1-7 requesting interrupt Processor Core IPL bits I/O Source I/O Source I/O Source Encoder 1 3 7 © Mark Redekopp, Al rights reserved Masking Interrupts in the Processor Core • May be times when we want the processor to execute important code and ignore (mask) interrupts • I-bits bits in SR accomplish this • Interrupt n will be ignored if n I-bits 0 0 1 0 101 000 1 0 1 0 1 SR: T S I-bits X N Z V C I-bits=5: Ignore interrupts [1-5] 0 0 1 000 000 1 0 1 0 1 SR: T S I-bits X N Z V C I-bits=0: Enable all interrupts 0 M 0 0 M © Mark Redekopp, Al rights reserved Non-Maskable Interrupt (NMI) • I-bits = 7 would normally mean ignore all interrupts (n will always be I) • Coldfire defines INT 7 as non-maskable – Cannot be ignored even if I = 7 • NMI is a safe guard to ensure some device can cause an interrupt no matter what.
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2 © Mark Redekopp, Al rights reserved Priority Inversion Problem • Normally, higher priority interrupt should be handled before lower priority interrupts – Example: INT 5 should be processed before INT 3 • Priority inversion occurs when a lower priority interrupt occurs during handling of a higher priority interrupt © Mark Redekopp, Al rights reserved Priority Inversion Problem .text MAIN --- --- (INT 5) --- --- .text ISR5 --- (INT 3) --- --- --- .text ISR3 --- --- --- --- ORG $1000 MAIN --- --- (INT 5) --- --- ORG $1100 ISR5 --- (INT 3 ignored) --- --- ORG $1200 ISR3 --- --- --- Set I=5 Restore I Restore I Set I=3 INT 3 interrupts ISR 5 and in effect INT 3 is handled before ISR 5 thus inverting the normal priority scheme. Solution: Raise I-bits = n on interrupt n (Raise it to 5 on INT 5 so that INT 3 will be ignored until ISR 5 completes) © Mark Redekopp, Al rights reserved Interrupt Processing When an interrupt occurs, the CPU finishes the current instruction and then automatically goes through a 6 step process: 1. Ignore interrupt if n I-bits 2. Make a copy of the SR and Return Address/PC
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EE357Unit10b_Interrupts - Coldfire M68K Interrupts EE 357...

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