EE357Unit11_MIPS_ISA

EE357Unit11_MIPS_ISA - Components of an ISA 1. Data and...

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1 © Mark Redekopp, Al rights reserved EE 357 Unit 11 MIPS ISA © Mark Redekopp, Al rights reserved Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible to the instructions Faster than accessing data from memory 4. Addressing Modes How instructions can specify location of data operands 5. Length and format of instructions How is the operation and operands represented with 1’s and 0’s © Mark Redekopp, Al rights reserved MIPS ISA RISC Style 32-bit internal / 32-bit external data size Registers and ALU are 32-bits wide Memory bus is logically 32-bits wide (though may be physically wider) Registers 32 General Purpose Registers (GPR’s) For integer and address values A few are used for specific tasks/values 32 Floating point registers Fixed size instructions All instructions encoded as a single 32-bit word Three operand instruction format (dest, src1, src2) Load/store architecture (all data operands must be in registers and thus loaded from and stored to memory explicitly) © Mark Redekopp, Al rights reserved MIPS Data Sizes Integer 3 Sizes Defined – Byte (B) • 8-bits – Halfword (H) • 16-bits = 2 bytes – Word (W) • 32-bits = 4 bytes Floating Point 2 Sizes Defined – Single (S) • 32-bits = 4 bytes – Double (D) • 64-bits = 8 bytes • (For a 32-bit data bus, a double would be accessed from memory in 2 reads)
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2 © Mark Redekopp, Al rights reserved MIPS GPR’s Assembler Name Reg. Number Description $zero $0 Constant 0 value $at $1 Assembler temporary $v0-$v1 $2-$3 Procedure return values or expression evaluation $a0-$a3 $4-$7 Arguments/parameters $t0-$t7 $8-$15 Temporaries $s0-$s7 $16-$23 Saved Temporaries $t8-$t9 $24-$25 Temporaries $k0-$k1 $26-$27 Reserved for OS kernel $gp $28 Global Pointer (Global and static variables/data) $sp $29 Stack Pointer $fp $30 Frame Pointer $ra $31 Return address for current procedure © Mark Redekopp, Al rights reserved MIPS Programmer-Visible Registers MIPS Core PC: $0 - $31 32-bits General Purpose Registers (GPR’s) Hold data operands or addresses (pointers) to data stored in memory Special Purpose Registers PC: Program Counter (32-bits) Holds the address of the next instruction to be fetched from memory & executed HI: Hi-Half Reg. (32-bits) For MUL, holds 32 MSB’s of result. For DIV, holds 32-bit remainder LO: Lo-Half Reg. (32-bits) For MUL, holds 32 LSB’s of result. For DIV, holds 32-bit quotient GPR’s Special Purpose Registers HI: LO: © Mark Redekopp, Al rights reserved MIPS Programmer-Visible Registers MIPS Core Coprocessor 0 Registers Status Register Holds various control bits for processor modes, handling interrupts, etc. Cause Register
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This note was uploaded on 04/03/2011 for the course EE 357 taught by Professor Mayeda during the Spring '08 term at USC.

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EE357Unit11_MIPS_ISA - Components of an ISA 1. Data and...

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