EE357Unit15_Single_Cycle_CPU

EE357Unit15_Single_Cycle_CPU - 11/11/10 CPU Organization...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
11/11/10 1 © Mark Redekopp and Gandhi Puvvada, Al rights reserved EE 357 Unit 15 Single-Cycle CPU Datapath and Control 1 © Mark Redekopp and Gandhi Puvvada, Al rights reserved CPU Organization Scope We will build a CPU to implement our subset of the MIPS ISA – Memory Reference Instructions: • Load Word (LW) • Store Word (SW) – Arithmetic and Logic Instructions: • ADD, SUB, AND, OR, SLT – Branch and Jump Instructions: • Branch if equal (BEQ) • Jump unconditional (J) These basic instructions exercise a majority of the necessary datapath and control logic for a more complete implementation 2 © Mark Redekopp and Gandhi Puvvada, Al rights reserved CPU Implementations 3 © Mark Redekopp and Gandhi Puvvada, Al rights reserved Single-Cycle Datapath To start, let us think about what operations need to be performed for the basic instructions All instructions go through the following steps: – Fetch: Use PC address to fetch instruction – Decode & Register/Operand Fetch: Determine instruction type and fetch any register operands needed Once decoded, different instructions require different operations – ALU instructions: Perform Add, Sub, etc. and write result back to register – LW / SW: Calculate address and perform memory access – BEQ / J: Update PC (possible based on comparison) Let us start with fetching an instruction and work our way through the necessary components 4
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
11/11/10 2 © Mark Redekopp and Gandhi Puvvada, Al rights reserved Fetch Components Required operations – Taking address from PC and reading instruction from memory – Incrementing PC to point at next instruction Components – PC register – Instruction Memory / Cache – Adder to increment PC value I-Cache / I-MEM Addr. Data From PC Instruction Word PC + A B CLK Write S Register Adder Memory 5 © Mark Redekopp and Gandhi Puvvada, Al rights reserved Fetch Datapath I-Cache / I-MEM Addr. Data Instruction Word PC A B CLK Write S 4 Current PC / Read Address “Next” PC = PC + 4 6 © Mark Redekopp and Gandhi Puvvada, Al rights reserved Fetch Datapath Example The PC and adder operation is shown – The PC doesn’t update until the end of the current cycle The instruction being read out from the instruction memory – We have shown “assembly” syntax and the field by field machine code breakdown I-Cache / I-MEM Addr. Data Instruction Word PC A B CLK Write S 4 Current PC / Read Address “Next” PC = PC + 4 (e.g. 0x012a8020) ADD $16,$9,$10 000000 01001 01010 00000 10000 100000 opcode rs rt shamt rd func 7 © Mark Redekopp and Gandhi Puvvada, Al rights reserved Fetch Datapath Question 1 Can the adder used to increment the PC be an ALU and be used/shared for ALU instructions like ADD/SUB/etc. – In a single-cycle CPU, resources cannot be shared thus we need a separate adder and separate ALU I-Cache / I-MEM Addr. Data Instruction Word PC A B CLK Write S 4 Current PC / Read Address “Next” PC = PC + 4 8
Background image of page 2
11/11/10 3 © Mark Redekopp and Gandhi Puvvada, Al rights reserved Fetch Datapath Question 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 11

EE357Unit15_Single_Cycle_CPU - 11/11/10 CPU Organization...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online