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Unformatted text preview: 11/12/10 1 © Mark Redekopp, Al rights reserved Multi-Cycle CPU Organization Datapath and Control © Mark Redekopp, Al rights reserved Single-Cycle CPU Datapath I-Cache PC + Addr. Instruc. Register File Read Reg. 1 # Read Reg. 2 # Write Reg. # Write Data Read data 1 Read data 2 Sign Extend ALU Res. Zero Sh. Left 2 + D-Cache Addr. Read Data Write Data A B 4 16 32 5 5 RegDst ALUSrc 5 MemtoReg MemWrite MemRead ALU control PCSrc Control RegWrite ALUSrc RegDst MemtoReg Branch MemRead & MemWrite INST[5:0] [31:26] [25:21] [20:16] [15:11] [15:0] ALUOp[1:0] ALUOp[1:0] © Mark Redekopp, Al rights reserved Multicycle CPU Implementation • Single cycle CPU sets the clock period according to the longest instruction execution time • Rather than making every instruction “pay” the worst case time, why not make each instruction “pay” just for what it uses – Example: Pay Parking • Parking meters: Cost proportional to time spent • Flat fee parking lot: One price no matter the time • Multicycle CPU implementation breaks instructions into smaller, shorter sub-operations – Clock period according to the longest sub-operation • Instructions like ADD or Jump with few sub-operations will take fewer cycles while more involved instructions like LW will take more cycles © Mark Redekopp, Al rights reserved Single vs. Multi-Cycle CPU • Single Cycle CPU design makes all instructions wait for the full clock cycle and the cycle time is based on the SLOWEST instruction • Multi-cycle CPU will break datapath into sub-operations with the cycle time set by the longest sub-operation. Now instructions only take the number of clock cycles they need to perform their sub-ops. Instruc. Fetch Decode / Reg. Fetch ALU Memory Access Write Result add lw CPI=1 Instruc. Fetch Decode / Reg. Fetch ALU Memory Access Write Result lw REG. REG. REG. REG. CPI=n Single-Cycle time time Multi-cycle 11/12/10 2 © Mark Redekopp, Al rights reserved Wasted Wasted Wasted Single-/Multi-Cycle Comparison In single-cycle implementations, the clock cycle time must be set for the longest instruction. Thus, shorter instructions waste time if they require a shorter delay. In multi-cycle CPU, each instruction is broken into separate short (and hopefully time- balanced) sub-operations. Each instruction takes only the clock cycles needed, allowing shorter instructions to finish earlier and have the next instruction start. CLK R-Type BEQ SW LW CLK R-Type BEQ SW LW Fetch / Reg. Read / ALU Op / Reg. Write Fetch / Reg. Read / Update PC Fetch / Reg. Read / Calc. Addr / Mem Write. Fetch / Reg. Read / Calc. Addr. / Mem Read / Reg. Write Fetch Reg. Read ALU Op Fetch Reg. Read Update PC Reg. Write Fetch Reg. Read Calc....
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- Spring '08
- Central processing unit, All rights reserved, Mark Redekopp, Instruc. Reg