EE357Unit4a_ColdfireISA

EE357Unit4a_ColdfireISA - 9/28/10 Instruction Set...

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Unformatted text preview: 9/28/10 Instruction Set Architecture (ISA) •  Defines the software interface of the computer system •  Instruction set is the “vocabulary” that the HW can understand and that SW is composed with •  2 approaches –  CISC = Complex instruction set computer (Coldfire/M68K & Intel) •  Large, rich vocabulary •  More work per instruction but slower HW EE 357 Unit 4a Instruction Set Architecture –  RISC = Reduced instruction set computer (MIPS / PPC / ARM) •  Small, basic, but sufficient vocabulary •  Less work per instruction but faster HW © Mark Redekopp, All rights reserved © Mark Redekopp, All rights reserved RISC & CISC Comparison •  Which is better? –  Exec. Time of a Program = Time to do all operations/work Computer Organization Overview •  A processor has to… –  Read instructions from memory –  Read necessary data into registers •  Fast storage locations inside the processor used to store values as the processor operates on them –  With CISC: (Work/Instruc.) = ↑ while (Time / Instruc.) ↑ –  With RISC: (Work/Instruc) = ↓ while (Time / Instruc.) ↓ –  Perform operations on the data –  Write data back to memory or I/O device Proc. Reg. Reg. Reg. ALU Mem. A D C8 C9 00 01 Inst. Inst. ... Data Data ... •  One is not inherently better, though most computers at the HW level implement RISC-style instructions because fewer operations per instruction makes the HW easier to design. © Mark Redekopp, All rights reserved © Mark Redekopp, All rights reserved 1 9/28/10 Components of an ISA 1.  Data and Address Size –  8-, 16-, 32-, 64-bit •  •  NEGate + ADD instrucs. •  Coldfire/M68K ISA CISC style 32-bit data and address –  –  –  –  •  •  2.  Which instructions does the processor support –  SUBtract instruc. vs. # of address bits determines max amount of memory Since addresses are also 32-bits => Max 4GB of memory 8 data registers (D0-D7) 8 address registers (A0-A7) Intended to store pointers (address to other data) Can be used for data 3.  Registers accessible to the instructions 4.  Addressing Modes –  How instructions can specify location of data operands Separate data and address registers 5.  Length and format of instructions –  How is the operation and operands represented with 1’s and 0’s •  –  Instructions = One 16-bit instruction word followed by 0-2 extension words stored after the instruction word Instruction word stores all information about operation and how to find the operands, while extension words are used depending on the specific instruction and store specific information used by the instruction © Mark Redekopp, All rights reserved © Mark Redekopp, All rights reserved Coldfire Processor Core Data & Address Registers (General-Purpose) Physical View of Main Memory •  Physical view of memory as large 2-D array of bytes –  (e.g. 8K rows by 1KB columns) per chip (and several chips) 32 •  Data Registers (32-bits) –  Hold data operands D0 - D7 A0 - A7 •  Address Registers (32-bits) –  Act like pointers to data in memory 32 •  Most computer memory is byte-addressable –  Each byte has a unique address •  Special Registers –  PC: Program Counter (32-bits) •  Holds the address of the next instruction to be executed 32 32 32 ALU Control •  Processor interfaces via address, data, and control buses PC: IR: SR: A 0x00000401 32 0x000000 0x000400 … ... ... ... ... –  IR: Instruction Reg. (16-bits) •  Holds the current instruction as it executes –  SR: Status Reg. (16-bits) •  Holds control bits and other “state” of the processor Proc. Coldfire Core Special Registers D 32 C Physical View of Memory © Mark Redekopp, All rights reserved © Mark Redekopp, All rights reserved 2 9/28/10 Coldfire Memory Interface •  Address bus = 32-bits •  Data bus = 32-bits –  Can read/write up to 4-bytes at once Address 0x000 0x004 5A 8E 13 29 F8 B4 7C 36 Instruction Format •  Instructions must specify three things: –  Operation (OpCode) –  Source operands & where to find them (reg. or mem.) •  Usually 2 source operands (e.g. X+Y) •  Memory can be read or written in 3 sizes –  –  –  –  1-byte (.B) 2-bytes = 1 word (.W) 4-bytes = 1 longword (.L) Always specify the start address & size and the memory will take the appropriate sequential bytes Logical View of Memory Organized as 4-byte (1 Longword) rows –  Destination Location (reg. or mem.) Longword @ Addr. 0 Word @ Addr. 0 Word @ Addr. 2 •  Example: ADD D0,D1,D2 (D0=D1+D2) •  Binary (machine-code) representation broken into fields of bits for each part •  Some instruction sets used F8 Byte @ 2 0x000 5A Byte @ 0 13 Byte @ 1 7C Byte @ 3 •  Valid words start @ addresses that is multiples of 2 •  Valid longwords start @ addresses that are multiples of 4 © Mark Redekopp, All rights reserved –  Fixed-size instructions (MIPS): all instruction encoded with same # of bits –  Variable-size instructions (Coldfire, Intel): differing lengths for different instructions OpCode Fictitious Example: © Mark Redekopp, All rights reserved Longword @ Addr. 4 Word @ Addr. 4 Word @ Addr. 6 Dest. 1000 D0 Src. 1 1001 D1 Src. 2 1010 D2 0x004 8E Byte @ 4 29 Byte @ 5 B4 Byte @ 6 36 Byte @ 7 1101 ADD Instruction Format •  Different instruction sets specify these differently –  3 operand instruction set (MIPS) •  Similar to example on previous page •  Format: ADD DST,SRC1,SRC2 (DST = SRC1 + SRC2) Instruction Format •  Consider the pros and cons of each format when performing the set of operations –  F = X + Y – Z –  G = A + B •  Embedded computers often use single operand format –  Smaller data size (8-bit or 16-bit machines) means limited instruc. size –  2 operand instructions (Coldfire/M68K & Intel/AMD) •  Second operand doubles as source and destination •  Format: ADD SRC1,S2/D (S2/D = SRC1 + S2/D) •  Today’s computers use 2- and 3-operand formats Single-Operand LOAD ADD SUB X Y Z Two-Operand MOVE ADD SUB MOVE ADD X,F Y,F Z,F A,G B,G Three-Operand ADD SUB ADD F,X,Y F,F,Z G,A,B –  1 operand instructions (Some low-end embedded) •  Implicit operand to every instruction usually known as the Accumulator (or ACC) register •  Format: ADD SRC1 (ACC = ACC + SRC1) STORE F LOAD A ADD B STORE G (+) Smaller size to encode each instruction (-) Higher instruction count to load and store ACC value © Mark Redekopp, All rights reserved Compromise of other two (+) More natural program style (+) Smaller instruction count (-) Larger size to encode each instruction © Mark Redekopp, All rights reserved 3 ...
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