_EE 425_Exp_7

_EE 425_Exp_7 - Electronic Circuits I Laboratory 7 JFET...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Electronic Circuits I Laboratory 7 JFET Characteristics 7.1 Objectives Understanding the basic characteristics of JFETs. 7.2 Basic Description 7.2.a Terminology JFET : The abbreviation of Junction Field Effect Transistor. G,D,S : Gate, Drain, Source. Vp, G gs (Cut-off) : Pinch-off voltage or cutoff voltage for G-S. I DSS : The saturation current for D-S. 7.2.b Basic Principle Transistor is a kind of current-control device, and its generating current includes electron flow and hole flow. The transistor is therefore referred to as bipolar junction transistor. FET is a unipolar device, in which the current of n-channel FET is formed by electron flow and the current of p-channel is formed by hole flow. FET is a kind of voltage-control device. FET can also perform the functions that general transistors (BJT) do, with the only exception that the bias conditions and characteristics are different. Their applications shall thus be chosen in accordance with related advantages and drawbacks. I The characteristics of FET are listed as follows: FET has very high input impedance, typically around 100 M . When FET is used as switch, there is no offset voltage. FET is relatively independent of radiation, whereas BJT is very sensitive to radiation ( β value will be varied). Intrinsic noise of FET is lower than BJT, which makes FET suitable for the input stage of low-Ievel amplifier During operation the thermal stability of FET is higher than that of BJT. However, FET also has some drawbacks: comparing with BJT, its product of gain and bandwidth is smaller and it is easier to be damaged by static electricity. 7.2.b.1 Structure and characteristics of JFET The internal structure of JFET is shown in Fig 7.1. The n-channel JFET is formed by difussing one pair of p-type region into a slab of n-type material. On the contrary, the p-channel JFET is formed by difussing one pair of n-type region into a slab of p-type material. In order to discuss the operation method of JFET, we hereby describe the bias arrangement applied to n-channel JFET as shown in Fig 7.2. The 60
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/05/2011 for the course ECON 550 taught by Professor Tracy during the Spring '10 term at Strayer.

Page1 / 8

_EE 425_Exp_7 - Electronic Circuits I Laboratory 7 JFET...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online