Lecture14_review_XBR0_PCA - Lecture#14 PCA/XBR0 review...

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Unformatted text preview: Lecture #14 PCA/XBR0 review - Blimp September 22, 2010 Crossbar Quiz 4 (next week) PCA and crossbar Configuring the PCA A number of SFRs are associated with the PCA to obtain a PWM signal Given XBR0=0Xnn; answer which pin, if any, while have TX0 or SDA or CEX2 Determine the correct value for XBR0 if you need to use UART0 and SPI0 but not SMB0 or any PCA pins. Variations of this line How to: to: Enable the PCA Enable the desired CCMs (Capture Compare Modules) Pick input signal Enable PCA overflow interrupts Clear the overflow flag in the interrupt service routine PCA Set the pulse width Determine the pulse width value in counts for a desired pulse width in msec Determine and write the correct value into the correct CCM (Capture Compare Module.) Do the above with correctly using SYSCLK or SYSCLK/4 or SYSCLK/12 Set the period the period Use the preset method to shorten the period Determine the correct preset value for a desired frequency (F) or desired period (T) F=1/T Given a preset value, determine the output frequency or period Given the above, what is the duty cycle of the output duty duty cycle = (on time / period)*100% PCA0CN: PCA0CN: Enable/disable the PCA PCA0MD: PCA0MD: Determine what will cause the counter to increment – the PCA mode PCA0CPMn: Determine the operating mode for the Capture/Compare Modules PCA0CPLn, PCA0CPHn: Store a value for the desired pulsewidth desired pulsewidth PCA0L, PCA0H: PCA0L, PCA0H: Store the current value of the PCA counter XBR0: XBR0: Assign the output pins to use with the PCA PCA_plotter isn’t allowed during the quiz 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 1 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 2 Configuring the PCA PCA0CN – PCA Control Register (Ch. 4, Pulsewidth Modulation) PCA0CN |= 0x40; PCA0CN X 1 X X X X X X Enable the counter – bit 6 Bit 6 = 1; The PCA counter is enabled Other bits are not changed, but the code maintains the historic value, only changing bit 6 Note: Bit 7 is set by overflows and is used for interrupts Lecture #14 PCA/XBR0 review - Blimp 4 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 3 9/22/2010 1 Lecture #14 PCA/XBR0 review - Blimp September 22, 2010 Configuring the PCA PCA0MD – PCA0 Counting Mode PCA0MD = 0x81; PCA0MD 1 0 0 0 0 0 0 1 Bit 0 = 1; Enables interrupt requests for the PCA Bit 1-3 = 000; PCA counts on system clock/12 1Bit 1; PCA operation suspended if the Bit 7 = 1; PCA operation suspended if the system system idles Other bits not important Lecture #14 PCA/XBR0 review - Blimp 6 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 5 9/22/2010 Configuring the PCA PCA0CPMn – PCAn Capture/ Compare Mode Registers (Ch. (Ch. 4, after Fig 4.5) PCA0CPM1 = 0xC2 PCA0CPM1; This is the SFR for CEX1 (why?) (why?) 1 1 0 0 0 0 1 0 We will use PCA0CPM0 PCA0CPM0 Set for 16-bit 16PWM, bit 7 Enable compare function bit function, bit 6 Enable Pulse Width Modulation Mode, bit 1 Bit 1 = 1; Enables a pulse width modulated (PWM) signal from the CEX1 port pin Bit 6 = 1; Enables the comparator so a high output is possible when the count passes the stored value Bit 7 = 1; 16 bit counting is used for the PWM Other bits not important Lecture #14 PCA/XBR0 review - Blimp 8 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 7 9/22/2010 2 Lecture #14 PCA/XBR0 review - Blimp September 22, 2010 Configuring the PCA PCA0L and PCA0H – Hold the current value of the PCA (pg 262 of SiLabs manual) the PCA (pg 262 of SiLabs manual) Configuring the PCA PCA0CPLn, PCA0CPLn, PCA0CPHn – Module 0 compare number (pg (pg 263 of SiLabs) SiLabs) Used to store the value at which desired action is to take place Two registers Two registers used used for the 8 low bits and the 8 high bits Two registers used for the 8 low bits and the 8 high bits 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 9 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 10 Crossbar (Figure 4.1) We need: TX0, RX0 for serial port, (printf and scanf scanf.) Configuring the PCA XBR0 – Port I/0 Crossbar Register 0 (Ch. 4, Figure 4.1) I2C bus – SDA, SCL (compass and ultrasonic ranger) PCA – CEX0, CEX1, CEX2, CEX3 (to be able to drive up to four motors.) Warning – Lab 3 has SPI enabled. For Lab 5 and 6 – it is off. SMB enable enable SPI enable UART0 enable CEXn enable 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 11 11 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 12 3 Lecture #14 PCA/XBR0 review - Blimp September 22, 2010 PCA Overflow Interrupt EIE1 – Extended Interrupt Enable 1 (Ch (Ch. 4, Programmable Counter Array) Programmable Counter Array) EIE1 |= 0x08; EA = 1; EA = 1; This setting is familiar to us from previous previous labs, it is necessary to enable all interrupts EIE1 |= 0x08 X Enable PCA0 interrupt – bit 3 X X X 1 X X X Bit Bit 3 is set to 1, the other bits maintain their th bit th previous values, this bit enables interrupt requests by PCA0 (note, multiple bits are set to enable PCA interrupts, as we have seen) Lecture #14 PCA/XBR0 review - Blimp 14 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 13 9/22/2010 Interrupt Number ((C8051 Man. pg. 117) C8051 Use the Priority Number that corresponds to the desired type of interrupt as the Interrupt number in the Interrupt function Interrupt Source Source Reset External Interrupt 0 (/INT0) Timer 0 Overflow External Interrupt 1 (/INT1) Timer 1 Overflow UART0 Timer 2 Overflow (or RXF2) Serial Peripheral Interface SMBus Interface ADC0 Window Comparator Programmable Counter Array Interrupt Vector 0x0000 0x0003 0x000B 0x0013 0x001B 0x0023 0x002B 0x0033 0x003B 0x0043 0x004B PCA Output Given the clock frequency, required period and pulsewidth and pulsewidth Priority Order Top 0 1 2 3 4 5 6 7 8 9 Interrupt Source Source Comparator 0 Falling Edge Comparator 0 Rising Edge Comparator 1 Falling Edge Comparator 1 Rising Edge Timer 3 Overflow ADC0 End of Conversion Timer 4 Overflow ADC1 End of Conversion External Interrupt 6 External Interrupt 7 UART1 External Crystal OSC Ready Interrupt Vector 0x0053 0x005B 0x0063 0x006B 0x0073 0x007B 0x0083 0x008B 0x0093 0x009B 0x00A3 0x00AB Priority Order 10 11 12 13 14 15 16 17 18 19 20 21 15 Calculate the PCA start value PCA0H PCA0L Calculate the Capture/Compare Module (CCM) threshold valued PCA0CPLn PCA0CPHn 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 16 4 Lecture #14 PCA/XBR0 review - Blimp September 22, 2010 Sample Problem Example: SYSCLK/4 SYSCLK/4 Initializations void PCA_Init () { PCA0MD = 0x83; PCA0CPM2 = 0xC2; PCA0CN |= 0x40; } void Interrupt_Init () { EIE1 |= 0x08; EA = 1; } void XBR0_Init () { XBR0 = 0x1D; } 17 9/22/2010 4.5 [ms] period 1.5 [ms] pulsewidth Enable UART0 Disable SPI Enable SMB UART1 is enabled Output on CEX2 // SYSCLK/4, enable CF interrupts, suspend // when idle // 16 bit, enable compare, enable PWM // enable PCA // enable PCA interrupts // enable all interrupts // set up URART0, SMB, and CEX 0-2 0- 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp Lecture #14 PCA/XBR0 review - Blimp 18 PCA Time/Overflow 1 1 4.5211227 108 seconds freq 22.1184 10 6 Hz for SYSCLK/4 the time per count is sysclckperiod seconds count Setting the PCA as a 16 bit counter, the total number of counts before an overflow is : 4 period 1.8084491 107 216 65536 counts The time between overflows is then 1.8084491 107 seconds 65536 counts 0.00118518 s 11.8518 ms for each overflow overflow overflow count Therefore, 65536 counts corresponds to 11.8518 ms PCA Values To determine the number of counts associated with the period and pulsewidth period counts _ period time _ overflow total _ counts for a 4.5 ms period when 65536 counts corresponds to 11.8518 ms counts _ period 4.5ms 11.8518ms 65536 counts _ period 24883 Similarly, to determine the pulsewidth pulsewidth counts _ pulsewidth time _ overflow total _ counts for a 1.5 ms pulsewidth when 65536 counts corresponds to 11.8518 ms 1.5ms counts _ pulsewidth 11.8518ms 65536 counts _ pulsewidth 8294 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 20 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 19 5 Lecture #14 PCA/XBR0 review - Blimp September 22, 2010 Capture/Compare Module Setting the PCA values Optional 2nd Problem PCA0CPL2 =0xFFFF-8294; =0xFFFF// 16 bit, enable compare, enable PWM PCA0CPH2 = (0xFFFF-8294)>>8; // 16 bit, enable compare, enable PWM (0xFFFFPCA start value PCA0L = (0xFFFF-24883); (0xFFFFPCA0H = (0xFFFF-24883)>>8; (0xFFFF// 16 bit, enable compare, enable PWM // 16 bit, enable compare, enable PWM Final Note: The output pin for CEX2 is P1.0 on pin 12 due to the specification to enable UART0, SMB0, & UART1 which pushes CEX0 to P0.6 (pin 14). 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 21 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 22 The PCA Interrupt Service Routine void PCA_ISR (void) interrupt 9 { if (CF) { nOverFlows++; PCA0L = PCA_start; // low byte of start count PCA0H = PCA_start>>8; // high byte of start count CF = 0; // Very important – clear interrupt flag } else PCA0CN &= 0xC0; // all other type 9 interrupts } The PCA ISR The previous code is called when the PCA overflows, that is when it reaches its maximum count count and resets to zero. For 16 bit counting, the ISR will be called when the counts switchs from 0xFFFF to 0x0000 In the ISR, three important actions take place 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 23 9/22/2010 1) A count variable is incremented (nOverflows) 2) The PCA is given a start value that corresponds to the desired period output for the CEX module (next slide) 3) The overflow flag is cleared (CF) Lecture #14 PCA/XBR0 review - Blimp 24 6 Lecture #14 PCA/XBR0 review - Blimp September 22, 2010 How do we pick PCA_Start From our experiences with Timer0 in Lab2, we know that when we use a 16 bit counter that counts counts every sysclk/12, it takes 35.5555 ms to sysclk/12, count from 0x0000 to 0xFFFF Therefore, if we are interested in setting a time period less than 35.5555 ms, we need to ms, determine the associated number of counts There are two ways to determine how many counts we need Example: 25 ms If we want to determine how many counts there are in 25 ms, we can use two simple formulas 1) n _ counts total _ time time _ count 2) n _ counts total _ time 65536 35.5555ms Lecture #14 PCA/XBR0 review - Blimp 26 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 25 9/22/2010 Example: 25 ms In the first formula we need to know the time per count, which is just sysclk/12 sysclk/12 In the second formula, we just correlate the relationship between total counts and total time n _ counts 25ms * 65536 46080counts 35.5555ms Therefore, for our configuration, 46080 counts of the PCA corresponds to 25 ms 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 27 In a human sense, we would start counting at 0 and when we reached 46080, we would know 20ms had passed passed However, our microcontroller offers features that allows us to act when it overflows at 0xFFFF If you think about counting for 15 seconds, there is no difference between 1) starting at 0 and counting to 15 2) starting at 45 and counting to 60 So, that is what we do, the PCA is set to start counting at (65536-46080) giving us a 20ms time period when it 65536reaches a count of 65536 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 28 Why computer counting is different 7 Lecture #14 PCA/XBR0 review - Blimp September 22, 2010 Setting the Capture/Compare Module A very similar type of calculation is necessary to set the CEX modules If we want the last 3 ms of our 25 ms period to be output high, we can determine the number of counts Setting the Capture/Compare Module PW = 65536-5530 65536PCA0CPL1 = 65525 - PW; // change pulse width PCA0CPH1 = (65525 - PW) >> 8; n _ counts 3ms * 65536 5530counts 35.5555ms Therefore, we need to set our comparator threshold to (65536-5530) counts This would correspond to 22 ms output low and 3 ms output high for the 25 ms period on CEX1 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 29 The above code sets the comparator Note: the “n”=“1” in the SFR PCA0CPLn and PCA0CPHn indica es you are se ing CEX1 cates you sett It is important that your CEX initialization and CEX comparator settings reference the same module 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 30 What XBR0 does The crossbar setting explicitly indicates which port pins are being used for which activities. A priority table (next slide) indicates how pins are reserved. Once XBR0 is set, the hardware wiring needs to be connected to the port pin indicated by the priority table. The hardware designer does not have the option of changing the port pin. 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 31 31 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp Crossbar pg 31 We need: TX0, RX0 for serial port, (printf and scanf scanf.) I2C bus – SDA, SCL (compass and ultrasonic ranger) PCA – CEX0, CEX1, CEX2, CEX3 (to be able to drive up to four motors.) Warning – this is different than past semesters. 32 32 8 Lecture #14 PCA/XBR0 review - Blimp September 22, 2010 How to read the priority table UART0 has the highest priority Configuring the PCA XBR0 – Port I/0 Crossbar Register 0 If it is enabled, it grabs P0.0 and P0.1 for TX0 and RX0. UART0 will always get those two port pins if it is enabled If it is enabled, it will grab the next 4 available port pins If UART0 was not enabled, SPI gets P0.0, P0.1, P0.2, P0.3 If UART0 was enable, SPI gets P0.2, P0.3, P0.4, P0.5 SPI had the next highest priority had the next highest priority SMB has the next highest priority If it is enabled, it will grab the next 2 available port pins If it is enabled, it will grab the next 2 available port pins, however in this class we will not use UART1 PCA will grab the number of pins based on how many CEX modules are specified (1-5, CEX0, CEX1, CEX2, CEX3, CEX4) (1Lecture #14 PCA/XBR0 review - Blimp 33 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 34 UART1 has the next highest priority has the next highest priority PCA has the next highest priority 9/22/2010 XBR0 = 0x27 0 0 1 0 0 1 1 1 Today and Next Class Today UART0: enabled, P0.0, P0.1 reserved SPI enabled, P0.2, P0.3, P0.4, P0.5 reserved SMB enabled, P0.6, P0.7 reserved PCA, 4 CEX modules enabled 9/22/2010 If you haven’t had a check off for Lab 3, part 2, do If you haven had check off for Lab 3, part 2, do so. so. Start work on Lab 3, part 3 Continue Lab 3, part 3 If you are behind, use open shop time to catch up. Next week we start Lab 4 -- compass and ranger pairs team up. up. Next class CEX0: P1.0 CEX1: P1.1 CEX2: P1.2 CEX3: P1.3 Lecture #14 PCA/XBR0 review - Blimp 35 Next week - Quiz 4 9/22/2010 Lecture #14 PCA/XBR0 review - Blimp 36 36 9 ...
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