Verilg HDL - Verilog Hardware Description Language Sections...

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1 Verilog Hardware Description Language Sections in Chapter 3-9 Digital Design, 4 th Edition M. Morris Mano and micchael D. Ciletti
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Introduction HDL stands for Hardware Description Language Used to describe digital system in textual form Oriented to the structure and behaviour of digital  systems Verilog HDL programs can be read by both  human and computer Tow main applications of HDL  Logic Simulation  Logic Synthesis 2
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Logic Simulation Representation of structure and behaviour of  digital systems using computer The simulator interrupts the HDL description  and produce readable output (table, timing  diagram, . .)  This process help in predicting how digital  system will behave before fabrication  The stimulus that test the design is called       Test Bench  (written in HDL) To simulate a digital system:-  Write the HDL description for the system  Verify using Test Bench  3
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Logic Synthesis Driving a list of components and its   interconnection (net list) from a module  described in HDL Used to fabricate integrated circuits or printed  circuit board  Same as conventional high level language, the  difference is it produce a database with  instruction how to fabricate the physical piece of  the digital system Source Code Conventional Lang Compilation Object Code 4
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Logic Synthesis (continue) Logic Synthesis Compilation Database with Instruction to Fabricate system Source   Code 5
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Historical Background Two main standard supported by IEEE VHDL Verilog HDL VHDL Developed by Department of defense Like  Ada  Programming language Verilog HDL By Cadence Data System (late1990) Easier than VHDL, like C language 6
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Simple Verilog HDL Example #1 Write a verilog HDL description for the  following circuit using gate level module  or_nand_1 (enable, x1, x2, x3, x4, y);    input   enable, x1, x2, x3, x4;    output   y;    wire   w1, w2, w3;     or   (w1, x1, x2);     or   (w2, x3, x4);     or   (w3, x3, x4);  // redundant     nand   (y, w1, w2, w3, enable); endmodule 7
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Simple Verilog HDL Example #2 Write a verilog HDL description for the  following circuit using Data flow module  or_nand_2 (enable, x1, x2, x3, x4, y);    input   enable, x1, x2, x3, x4;   output   y;   assign   y = !(enable & (x1 | x2) & (x3 | x4)); endmodule 8
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Write a verilog HDL description for the  following circuit using behavioral module  or_nand_3 (enable, x1, x2, x3, x4, y);     input   enable, x1, x2, x3, x4;     output   y;      reg   y;     always   @   (enable  or   x1  or                         x2 
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Verilg HDL - Verilog Hardware Description Language Sections...

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