Unformatted text preview: MATECH’s Future Factory Design Methodology,” Proceedings of the Advanced Semiconductor Manufacturing Conference, Boston, MA. AUTHOR BIOGRAPHIES Robert C. Kotcher received his B.S. degree in Industrial & Systems Engineering from San Jose State University, San Jose, California, in 1983, and his MBA degree from Santa Clara University, Santa Clara, California, in 1999. He is currently an industrial engineer for Headway Technologies, specializing in capacity planning and fab simulation. Dr. Frank Chance is a recognized expert in the modeling and simulation of complex manufacturing facilities. He is the author of Factory Explorer®, an integrated capacity, cost, and simulation analysis tool. He is a co-founder and principal of FabTime Inc. His clients in the semiconductor industry have included Seagate, Siemens, Headway, and IBM. Dr. Chance holds MS and Ph.D. degrees in Operations Research from Cornell University. He has taught at Cornell University and was a visiting assistant professor at the University of California, Berkeley, prior to founding Chance & Robinson. ACKNOWLEDGEMENTS The authors would like to thank Jennifer Robinson of FabTime Inc. and Steven Brown of Infineon for their contributions. 2. In ways such as these, this method allows Headway to take the first step beyond traditional capacity planning. Where capacity planning answers the question “What capital © 1999 IEEE. Reprinted, with permission, from Proceedings of the 1999 IEEE International Symposium on Semiconductor Manufacturing Conference, Santa Clara, CA, October 11-13, 1999, 73-76. 4...
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- Spring '11
- Semiconductor device fabrication, Headway, tool group