L2_pipeline_2010

L2_pipeline_2010 - Computer Architecture MIPS Pipeline Dr....

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Computer Architecture 2010– Pipeline 1 Computer Architecture MIPS Pipeline Dr. Lihu Rappoport Some of the slides were taken from: (1) Avi Mendelson (2) Randi Katz (3) Patterson
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Computer Architecture 2010– Pipeline 2 Data Access Data Access Data Access Data Access Data Access Pipelining Instructions Ideal speedup is number of stages in the pipeline. Do we achieve this? 2 4 6 8 10 12 14 16 18 2 4 6 8 ... Inst Fetch Reg ALU Reg Inst Fetch Reg ALU Reg Inst Fetch Inst Fetch Reg ALU Reg Inst Fetch Reg ALU Reg Inst Fetch Reg ALU Reg 2 ns 2 ns 2 ns 2 ns 2 ns 2 ns 2 ns 8 ns 8 ns 8 ns Time Program execution order lw R1, 100(R0) lw R2, 200(R0) lw R3, 300(R0) Time Program execution order lw R1, 100(R0) lw R2, 200(R0) lw R3, 300(R0)
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Computer Architecture 2010– Pipeline 3 Pipelined Car Assembly chassis engine finish 1 hour 2 hours 1 hour Car 1 Car 2 Car 3
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Computer Architecture 2010– Pipeline 4 Pipelining Pipelining does not reduce the latency of single task, it increases the throughput of entire workload Potential speedup = Number of pipe stages Pipeline rate is limited by the slowest pipeline stage Partition the pipe to many pipe stages Make the longest pipe stage to be as short as possible Balance the work in the pipe stages Pipeline adds overhead (e.g., latches) Time to “fill” pipeline and time to “drain” it reduces speedup Stall for dependencies Too many pipe-stages start to loose performance IPC of an ideal pipelined machine is 1 Every clock one instruction finishes
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Computer Architecture 2010– Pipeline 5 Instruction Decode / register fetch Instruction fetch Execute / address calculation Memory access Write back ALUSrc 6 ALU result Zero Add result Add Shift left 2 ALU Control ALUOp RegDst RegWrite Read reg 1 Read reg 2 Write reg Write data Read data 1 Read data 2 Register File [15-0] [20-16] [15-11] Sign extend 16 32 ID/EX EX/MEM MEM/WB Instruction MemRead MemWrite Address Write Data Read Data Data Memory Branch PCSrc MemtoReg 4 Instruction Memory Address Add IF/ID PC 0 1 m u x 0 1 m u x 0 1 m u x 1 0 m u x Instruction Pipelined CPU
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Computer Architecture 2010– Pipeline 6 Pipelined CPU with Control ALUSrc 6 ALU result Zero Add result Add Shift left 2 ALU Control ALUOp RegDst RegWrite Read reg 1 Read reg 2 Write reg Write data Read data 1 Read data 2 Register File [15-0] [20-16] [15-11] Sign extend 16 32 ID/EX EX/MEM MEM/WB Instruction MemRead MemWrite Address Write Data Read Data Data Memory Branch PCSrc MemtoReg 4 Instruction Memory Address Add IF/ID PC 0 1 m u x 0 1 m u x 0 1 m u x 0 1 m u x Instruction Control WB MEM WB MEM WB EXE Instruction Decode / register fetch Instruction fetch Execute / address calculation Memory access Write back
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Computer Architecture 2010– Pipeline 7 Structural Hazard Attempt to use the same resource two different ways at the same time Register File : Accessed in 2 stages: Read during stage 2 (ID) Write during stage 5 (WB) Solution: 2 read ports, 1 write port Memory Accessed in 2 stages: Instruction Fetch during stage 1 (IF)
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This note was uploaded on 04/14/2011 for the course CS 234267 taught by Professor Rapaport during the Spring '07 term at Technion.

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L2_pipeline_2010 - Computer Architecture MIPS Pipeline Dr....

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