L5_BR_PRED_2010

L5_BR_PRED_2010 - Computer Architecture Advanced Branch...

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Computer Architecture 2010 – Branch Prediction 1 Computer Architecture Advanced Branch Prediction Lihu Rappoport and Adi Yoaz
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Computer Architecture 2010 – Branch Prediction 2 Introduction Need to predict: Conditional branch direction (taken or no taken) Actual direction is known only after execution Wrong direction prediction causes a full flush All taken branch (conditional taken or unconditional) targets Target of direct branches known at decode Target of indirect branches known at execution Branch type Conditional, uncond. direct, uncond. indirect, call, return Target: minimize branch misprediction rate for a given predictor size
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Computer Architecture 2010 – Branch Prediction 3 What/Who/When We Predict/Fix Fetch Decode Execute Target Array Branch type conditional unconditional direct unconditional indirect call return Branch target Indirect Target Array Predict indirect target override TA target Return Stack Buffer Predict return target Cond. Branch Predictor Predict conditional T/NT Fix TA miss Fix wrong direct target on TA miss try to fix Fix TA miss Fix Wrong prediction Fix Wrong prediction Fix Wrong prediction Dec Flush Exe Flush
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Computer Architecture 2010 – Branch Prediction 4 Branches and Performance MPI : misprediction-per-instruction: # of incorrectly predicted branches MPI = total # of instructions MPI correlates well with performance. For example: MPI = 1% (1 out of 100 instructions @1 out of 20 branches) IPC=2 (IPC is the average number of instructions per cycle), flush penalty of 10 cycles We get: MPI = 1% flush in every 100 instructions flush in every 50 cycles (since IPC=2), 10 cycles flush penalty every 50 cycles 20% in performance
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Computer Architecture 2010 – Branch Prediction 5 Target Array TA is accessed using the branch address (branch IP) Implemented as an n -way set associative cache Tags usually partial Save space Can get false hits Few branches aliased to the same entry No correctness only performance TA predicts the following Indication that instruction is a branch Predicted target Branch type Unconditional: take target Conditional: predict direction TA allocated / updated at execution Branch IP tag target predicted target hit / miss (indicates a branch) type predicted type
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Computer Architecture 2010 – Branch Prediction 6 Conditional Branch Direction Prediction
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Computer Architecture 2010 – Branch Prediction 7 One-Bit Predictor Problem: 1-bit predictor has a double mistake in loops Branch Outcome 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 Prediction ? 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 branch IP Prediction (at fetch): previous branch outcome counter array / cache Update (at execution) Update bit with branch outcome
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Computer Architecture 2010 – Branch Prediction 8 Bimodal (2-bit) Predictor A 2-bit counter avoids the double mistake in glitches Need “more evidence” to change prediction
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This note was uploaded on 04/14/2011 for the course CS 234267 taught by Professor Rapaport during the Spring '07 term at Technion.

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L5_BR_PRED_2010 - Computer Architecture Advanced Branch...

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