{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

L11_PC_2010 - Dr.LihuRappoport 1 Computer Architecture 2010...

Info icon This preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
Computer Architecture 2010 – PC Structure and Peripherals 1 Computer Architecture Computer Architecture         PC Structure and Peripherals PC Structure and Peripherals Dr. Lihu Rappoport
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Computer Architecture 2010 – PC Structure and Peripherals 2 Memory Memory
Image of page 2
Computer Architecture 2010 – PC Structure and Peripherals 3 Capacity Speed Logic in 3 years 2× in 3 years DRAM 4× in 3 years 1.4× in 10 years Disk 2× in 3 years 1.4× in 10 years Technology Trends Technology Trends CPU-DRAM Memory Gap (latency) 1 10 100 1000 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU Performance Time
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Computer Architecture 2010 – PC Structure and Peripherals 4 SRAM vs. DRAM SRAM vs. DRAM Random Access: access time is the same for all locations DRAM – Dynamic RAM SRAM – Static RAM Refresh Regular refresh (~1% time) No refresh needed Address  Address muxed: row+ column Address not multiplexed Access Not true “Random Access” True “Random Access” density High (1 Transistor/bit) Low (6 Transistor/bit) Power low high Speed slow fast Price/bit low high Typical usage Main memory cache
Image of page 4
Computer Architecture 2010 – PC Structure and Peripherals 5 Basic DRAM chip Basic DRAM chip Addressing sequence Row address and then RAS# asserted RAS# to CAS# delay Column address and then CAS# asserted DATA transfer Row latch Row address decoder Column addr decoder Column latch CAS# RAS# Data Memory array Memory address bus Addr
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Computer Architecture 2010 – PC Structure and Peripherals 6 Addressing sequence Addressing sequence Access sequence Put row address on data bus and assert RAS# Wait for RAS# to CAS# delay (t RCD ) Put column address on data bus and assert CAS# DATA transfer Precharge t RAC –Access time RAS/CAS delay Precharge delay RAS# Data A[0:7] CAS# Data n Row i Col n Row j X CL - CAS latency X
Image of page 6
Computer Architecture 2010 – PC Structure and Peripherals 7 DRAM Timing DRAM Timing CAS Latency: #clock cycles to access a specific column of data #clock cycle from the moment memory controller issues a column in the  current row, and the data is read out from memory RAS to CAS Delay: #clock cycles between row and column access Row Pre-charge time: #clock cycles to close an open row, and open  the next row Active to Precharge Delay #clock cycles to access a specific row  between the data request and the pre-charge command.
Image of page 7

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Computer Architecture 2010 – PC Structure and Peripherals 8 Basic SDRAM controller Basic SDRAM controller     DRAM address decoder Time delay gen. address mux RAS# CAS# R/W# A[20:23] A[10:19] A[0:9] Memory address bus D[0:7] Select Chip select DRAM data must be periodically refreshed Needed to keep data correct DRAM controller performs DRAM refresh, using refresh counter
Image of page 8
Computer Architecture 2010 – PC Structure and Peripherals 9 Paged Mode DRAM
Image of page 9

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern