L11_PC_2010

L11_PC_2010 - ComputerArchitecture...

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Computer Architecture 2010 – PC Structure and Peripherals 1 Computer Architecture Computer Architecture         PC Structure and Peripherals PC Structure and Peripherals Dr. Lihu Rappoport
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Computer Architecture 2010 – PC Structure and Peripherals 2 Memory Memory
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Computer Architecture 2010 – PC Structure and Peripherals 3 Capacity Speed Logic in 3 years 2× in 3 years DRAM 4× in 3 years 1.4× in 10 years Disk 2× in 3 years 1.4× in 10 years Technology Trends Technology Trends CPU-DRAM Memory Gap (latency) 1 10 100 1000 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU Performance Time
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Computer Architecture 2010 – PC Structure and Peripherals 4 SRAM vs. DRAM SRAM vs. DRAM Random Access: access time is the same for all locations DRAM – Dynamic RAM SRAM – Static RAM Refresh Regular refresh (~1% time) No refresh needed Address  Address muxed: row+ column Address not multiplexed Access Not true “Random Access” True “Random Access” density High (1 Transistor/bit) Low (6 Transistor/bit) Power low high Speed slow fast Price/bit low high Typical usage Main memory cache
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Computer Architecture 2010 – PC Structure and Peripherals 5 Basic DRAM chip Basic DRAM chip Addressing sequence Row address and then RAS# asserted RAS# to CAS# delay Column address and then CAS# asserted DATA transfer Row latch Row address decoder Column addr decoder Column latch CAS# RAS# Data Memory array Memory address bus Addr
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Computer Architecture 2010 – PC Structure and Peripherals 6 Addressing sequence Addressing sequence Access sequence Put row address on data bus and assert RAS# Wait for RAS# to CAS# delay (t RCD ) Put column address on data bus and assert CAS# DATA transfer Precharge t RAC –Access time RAS/CAS delay Precharge delay RAS# Data A[0:7] CAS# Data n Row i Col n Row j X CL - CAS latency X
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Computer Architecture 2010 – PC Structure and Peripherals 7 DRAM Timing DRAM Timing CAS Latency: #clock cycles to access a specific column of data #clock cycle from the moment memory controller issues a column in the  current row, and the data is read out from memory RAS to CAS Delay: #clock cycles between row and column access Row Pre-charge time: #clock cycles to close an open row, and open  the next row Active to Precharge Delay #clock cycles to access a specific row  between the data request and the pre-charge command.
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Computer Architecture 2010 – PC Structure and Peripherals 8 Basic SDRAM controller Basic SDRAM controller     DRAM address decoder Time delay gen. address
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This note was uploaded on 04/14/2011 for the course CS 234267 taught by Professor Rapaport during the Spring '07 term at Technion.

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L11_PC_2010 - ComputerArchitecture...

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