Lec_12 - Lecture 12: Digital Controller Design Using Root...

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Unformatted text preview: Lecture 12: Digital Controller Design Using Root Locus • Phase-Lead Compensation • Phase-Lag Compensation • Lag-Lead Compensation • Reading: Chapter 8 Digital Controller Design Process • Design is the process of find suitable digital compensators to achieve desired performance specifications • Commonly used compensators – – – – Phase-lead compensator Phase-lag compensator Lag-lead compensator PID compensators • Design methods: manual, root-locus, frequency-response, state-model, computer-aided design • Multiple design iterations may be needed for satisfactory performance 1 Compensation by Digital Controllers Original (uncompensated) system: R(s) + T G(s) C (s) ¡ H (s) Transfer function: C (z ) R(z ) = G(z ) 1+GH (z ) System with digital controller (compensator) R(s) + T D(z ) G(s) C (s) ¡ H (s) Transfer function: R(z ) = 1+D(z )GH (z) C (z ) D(z )G(z ) Inner Loop Digital Compensation R(s) + T G1 (s) + ¡ ¡ G2(s) T C (s) H2 (s) D(z ) H1 (s) Digital compensator D(z) is employed in the inner loop of the feedback system (minor-loop compensation). 2 Typical Design Objectives • To stabilize the system (or increase stability margin) • To improve the system transient response • To decrease the steady-state tracking errors • To make the system more robust to parameter variations and external perturbations • To improve system efficiency To Improve System Stability • Stability is the primary design concern of any practical system • Stability is often characterized by • Locations of the closed-loop poles • Stability margin: gain margin and phase margin • Suitable design of digital controllers can improve stability • Make an originally unstable system stable (stabilization) • Increase stability margins • Sometimes at odd with other objectives 3 To Improve System Transient Response • Response of a system is largely determined by the locations of its closed-loop poles, especially the dominant poles – For continuous-time systems, poles furthest to the right – For sampled-data systems, poles furthest from the origin • Some commonly used response specifications – Maximum overshoot Mp – Settling time ts – Peak time, rise time, etc. • By adjusting the parameters in the digital controller, one can move dominant poles towards the desired locations – Often analyzed using root locus method To Decrease Steady-State Tracking Errors R(s) + T D(z ) G(s) = ¡ 1 s+1 C (s) G(z ) = Type 0 system, with ess=0.5 for unit step input and ess=1 for unit ramp input z With a digital compensator D(z) = Kd z¡1 1¡e¡T z¡e¡T Compensated system is of type 1, with ess = 0 for unit step input T ess = Kd for unit ramp input 4 For Better Disturbance Rejection disturbance F (s) R(s) + T D(z ) G1 (s) + + G2 (s) C (s) ¡ C (z ) = D(z )G1 G2 (z ) R(z ) 1+D(z )G1 G2 (z) + G2 F (z) 1+D(z )G1 G2 (z) Due to input Due to disturbance By choosing the compensator D(z)=Kd with a large Kd, the effect of disturbance can be significantly reduced without affecting the tracking performance. To Increase Efficiency • In practical applications, everything including the control input comes at a cost • Find the compensator satisfying all the performance specifications while minimizing control cost • Optimal control problem 5 Commonly Used Compensators • Proportional compensator • First Order Compensator: D(z) = Kd z¡z0 D(z) = Kd z¡zp • Depending on the choice of z0 and zp, we can have – Phase-Lag Compensator (low pass filter): z0<zp<1 – Phase-Lead Compensator (high pass filter): zp<z0<1 • Lag-lead compensator is a composition of phase-lead and phase-lag compensators • PID Controller Digital Controller Design Using Root Locus 6 s-Plane Specifications (s-grids) H (s) = has two poles p1;2 = ¡¾ § j !d Damping ratio: ³ Undamped natural frequency: 2 !n 2+2³ !ns+! 2 s n 1 0.4 0.30.20.1 0.5 0.6 0.8 0.7 0.6 0.8 0.9 p1 !n !d = q £ 0.4 1 ¡ ³ 2!n !n ¯ 0.2 µ ¾ = ³ !n 0.2 Settling time (2%) 4 ts ' !n 0.9 ³ 1¡³ 2 Maximum overshoot Mp = e ¡p ¼ p2£ 0.4 0.6 0.8 0.7 0.6 0.8 0.5 0.30.20.1 0.4 1 z-Plane Specifications (z-grids) 1 0.6 /T 0.8 0.7 /T 0.5 /T 0.4 /T 0.1 0.3 /T ³ 0.6 0.8 /T 0.4 0.9 /T 0.2 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.1 /T 0.2 /T >> zgrid; 0 /T /T -0.2 0.9 /T -0.4 0.1 /T -0.6 0.8 /T 0.2 /T -0.8 0.7 /T 0.6 /T 0.4 /T 0.5 /T 0 0.3 /T -1 -1 -0.5 0.5 1 7 Deriving z-Plane Specifications • Given a set of time specifications, such as maximum overshoot, settling time, rise time, etc. • Determine the desired ³ and !n • From the z-grids, find the desired locations p* of the dominant poles of the compensated discrete-time system Example Design Specifications (T=0.5): 1 0.8 0.7 /T 0.5 /T 0.6 /T 0.4 /T 0.1 0.3 /T 0.2 Mp=16.3 % 0.6 0.8 /T 0.3 0.4 0.5 0.2 /T ) ³ = 0:5 0.4 0.9 /T 0.2 0.6 0.7 0.8 0.9 /T /T 0.1 /T ts<10 (2% criterion) 0 ) ³ !n > 0:4 -0.2 ) jpj < e¡0:4T 0.9 /T -0.4 0.1 /T -0.6 0.8 /T 0.2 /T -0.8 0.7 /T 0.6 /T 0.4 /T 0.5 /T 0 0.3 /T -1 -1 -0.5 0.5 1 8 Phase-Lead Compensation Example: An Uncompensated System R(s) + T = 0:1 G(s) C (s) ¡ G(s) = 1 1¡e¡T s K s s(s+1) Root Locus G(z) = 0:004837K(z+0:9672) (z¡1)(z¡0:9048) For K=0.244, the system has a double closed-loop pole at: p1;2 = 0:952 Unit step response 0.8 0.6 1 0.9 0.4 0.2 Imaginary Axis System: G Gain: 0.244 Pole: 0.952 Damping: 1 Overshoot (%): 0 Frequency (rad/sec): 0.0494 0.8 0.7 0.6 0.5 0 -0.2 0.4 -0.4 0.3 0.2 0.1 -0.6 -0.8 0 -1 -1 -0.8 -0.6 -0.4 -0.2 0 Real Axis 0.2 0.4 0.6 0.8 1 0 2 4 6 8 10 12 9 Design Problem I R(s) + T = 0:1 D(z ) G(s) C (s) ¡ G(z) = 0:004837K(z+0:9672) (z¡1)(z¡0:9048) (K=0.244) Objective: Design the digital controller D(z) so that the closed-loop system has a double dominant pole at p¤ = 0:844 Root Locus 1 0.8 0.6 0.4 Imaginary Axis Settling time for uncompensated system: ts = 8:12 s Settling time for compensated system: ¤ p ¤ 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 ts = 2:36 s -1 -0.5 0 Real Axis 0.5 1 A Simple Solution Design the digital compensator of the form z¡z0 D(z ) = Kd z¡zp so that the introduced zero z0=0.9048 cancels one of the original open-loop poles Root Locus 1 0.8 0.6 0:904 D(z ) = 10:5 z¡¡0:7 8 z System: untitled1 Gain: 10.5 Pole: 0.844 + 8.13e-008i Damping: 1 Overshoot (%): 0 Frequency (rad/sec): 0.17 0.4 0.2 Imaginary Axis 0 -0.2 -0.4 -0.6 -0.8 -1 -1 -0.8 -0.6 -0.4 -0.2 0 Real Axis 0.2 0.4 0.6 0.8 1 10 Comparison of Step Responses Step Response 1 0.9 0.8 0.7 0.6 Amplitude 0.5 0.4 0.3 0.2 0.1 0 compensated uncompensated 0 20 40 60 Samples 80 100 120 0:904 D(z ) = 10:5 z¡¡0:7 8 z Phase-Lead Compensation • Problem: given a closed-loop system, we wish to improve its dynamic characteristics, such as time constant, settling time, maximum overshoot • Normally a simple proportional controller is not enough • Solution: use a phase-lead compensator of the form z¡z0 D(z ) = Kd z¡zp (zp < z0 < 1) to bend the root locus of the original system • Compare with continuous-time phase-lead compensator s¡s0 C (s) = Kd s¡sp (sp < s0 < 0) 11 Designing Phase-Lead Compensator R(s) + T D(z ) G(s) C (s) ¡ z¡z0 D(z ) = Kd z¡zp ) G(z) = K (z¡z1 )¢¢¢¢¢¢(z¡zm) (z¡p1 ) (z¡pn Goal: the desirable closed-loop pole of the compensated system is at p* , which is not on the root locus of the uncompensated system Solution: find Kd, z0, and zp such that 1 + D(p¤)G(p¤) = 0 p ¡z0 , 1 + Kd p¤ ¡zp G(p¤) = 0 ¤ p¤ Á , [6 (p¤ ¡ z0 ) ¡ 6 (p¤ ¡ zp)] = 180± ¡ 6 G(p¤) Á: angle of deficiency zp £ ± z0 Find zp and z0 geometrically (see right figure) Kd can be found by using the magnitude condition Design Problem II R(s) + T = 0:1 D(z ) 0:004837K(z+0:9672) (z¡1)(z¡0:9048) G(s) C (s) ¡ G(z) = (K=0.244) Objective: Design the digital controller D(z) so that the system has a dominant closed-loop pole at p¤ = 0:4 + j 0:4 (³ = 0:6) Root Locus 1 0.8 0.6 0.4 Imaginary Axis 6 G(p¤) = 88:39± p¤ ¤ ) Á = 91:60± Set z0 = 0:85 zp = 0:024 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 Kd = 250 ¡0 D(z ) = 250 zz¡0::85 024 -1 -0.5 0 Real Axis 0.5 1 12 Compensated System R(s) + T = 0:1 D(z ) ¡0 D(z ) = 250 zz¡0::85 024 Root Locus G(s) 0:004837K(z+0:9672) (z¡1)(z¡0:9048) C (s) ¡ G(z) = (K=0.244) 1 0.8 0.6 System: untitled1 Gain: 250 Pole: 0.4 + 0.396i Damping: 0.593 Overshoot (%): 9.87 Frequency (rad/sec): 0.968 0.4 0.2 Imaginary Axis 0 -0.2 -0.4 -0.6 -0.8 -1 -1 -0.8 -0.6 -0.4 -0.2 0 Real Axis 0.2 0.4 0.6 0.8 1 Comparison of Step Responses Step Response 1.4 1.2 compensated 1 Amplitude 0.8 0.6 0.4 uncompensated 0.2 0 0 20 40 60 Samples 80 100 120 13 Phase-Lag Compensation Example: An Uncompensated System R(s) + T =1 G(s) C (s) ¡ G(s) = 1¡e¡T s 0:3812 s s(s+1) ) G(z) = 0:1442(z+0:717) (z¡1)(z¡0:368) Closed-loop poles locations: : (z+0 717) 1 + G(z) = 1 + 0z1442(z¡0::368) = 0 ( ¡1) ) p1;2 = 0:6119 § j 0:3114 Type 1 system, with Kdc = 0:3918 14 Root Locus of the Uncompensated System R(s) + T =1 D(z ) G(s) C (s) ¡ A system with open loop transfer function G(z) = 0:1442(z+0:717) (z¡1)(z¡0:368) Root Locus 1 0.6 /T 0.8 0.7 /T 0.5 /T 0.4 /T 0.1 0.3 /T 0.2 0.6 0.3 0.8 /T 0.4 0.5 0.6 0.9 /T 0.2 Imaginary Axis A proportional compensator D(z) = K 0.4 System: sys Gain: 1 Pole: 0.606 + 0.311i 0.2 /T Damping: Overshoot (%): Frequency (rad/sec): 0.1 /T 0.7 0.8 0.9 0 /T /T -0.2 0.9 /T -0.4 0.8 /T 0.2 /T 0.1 /T -0.6 By setting K=1, we get the original uncompensated system -0.8 0.7 /T 0.6 /T 0.4 /T 0.5 /T -1 -0.5 0 Real Axis 0.3 /T -1 0.5 1 Design Problem • Suppose we are satisfied with the dynamic characteristics of the system, but not its steady-state error performance • Problem: we want to decrease the original system’s steadystate error, without changing its dominant closed-loop pole location appreciably • A simple proportional controller won’t be enough • Solution: use a phase-lag compensator 15 Phase-Lag Compensator • A phase-lag compensator is of the form z¡z0 D(z ) = Kd z¡zp (0 < z0 < zp < 1) where both the zero z0 and the pole zp are very close to 1 • Compare with continuous-time phase-lag compensator s¡s0 (s0 < sp < 0) C (s) = Kd s¡sp where both s0 and sp are very close to 0 • Properties of phase-lag compensator (by using Kd=1) – No significant modification of root locus of the original system away from 1 1¡z0 – Increase the steady-state error constant by a factor of 1¡zp > 1 Design Example R(s) + T =1 D(z ) G(s) C (s) ¡ G(z) = 0:1442(z+0:717) (z¡1)(z¡0:368) Decrease the steady-state error for tracking unit ramp input to 1/10 of the uncompensated system without changing its dominant closed -loop locations Phase-lag compensator: D(z ) = z¡z0 z ¡zp (0 < z0 < zp < 1) satisfying both z0 and zp are close to 1 and 1¡z0 1¡zp = 10 One example: z0 = 0:99, zp = 0:999 16 Compensated System G(z) = D (z ) = 1 0:1442(z+0:717) (z¡1)(z¡0:368) z ¡0:99 z ¡0:999 Root Locus 14 : : Characteristic equation: 1 + (0:¡14)2(z+03717)(z¡0999)) = 0 z (z¡0: 68)(z¡0: 99 Closed-loop poles: p1 = 0:6165 + j 0:3078 p2 = 0:6165 ¡ j 0:3078 p3 = 0:9898 0.8 System: untitled1 Gain: 1 Pole: 0.61 + 0.307i Damping: 0.634 Overshoot (%): 7.63 Frequency (rad/sec): 0.602 0.6 0.4 p1,2 determine largely the response 0.2 Imaginary Axis 0 Root Locus -0.2 0.015 0.01 -0.4 0.005 Imaginary Axis -0.6 0 -0.8 -0.005 -0.01 -1 -1 -0.8 -0.6 -0.4 -0.2 0 Real Axis 0.2 0.4 0.6 0.8 1 -0.015 0.98 0.985 0.99 Real Axis 0.995 1 Unit Step Responses Step Response 1.4 1.4 Step Response 1.2 1.2 1 1 Amplitude 0.6 Amplitude 0.8 0.8 0.6 0.4 0.4 0.2 0.2 0 0 5 10 Time (sec) 15 20 25 0 0 5 10 Time (sec) 15 20 25 Uncompensated system Compensated system (longer horizon below) Step Response 1.4 1.2 1 Amplitude 0.8 0.6 0.4 0.2 0 0 50 Time (sec) 100 150 17 Unit Ramp Responses Uncompensated system Impulse Response 50 45 40 35 Amplitude Amplitude Compensated system Impulse Response 50 45 40 35 30 25 20 15 10 5 0 30 25 20 15 10 5 0 0 5 10 15 20 25 30 n (samples) Impulse Response 35 40 45 0 5 10 15 20 25 30 n (samples) ramp response 35 40 45 498.5 498 497.5 497 501 Longer horizon 500.5 500 499.5 Longer horizon Amplitude 496.5 496 495.5 Amplitude 497.5 498 498.5 499 Time (sec) 499.5 500 500.5 501 499 498.5 498 495 497.5 494.5 497 494 497 496.5 497 497.5 498 498.5 499 Time (sec) 499.5 500 500.5 501 Summary of Phase Lag Compensator • Phase-lag compensator can reduce system’s steady-state errors without changing its dominant poles’ locations much • Phase-lag compensator introduces a closed-loop pole near 1, resulting in a small yet persistent response in step response • Phase-lead compensator can be combined with phase-lad compensator to form the Lag-Lead Compensator: z ¡z0 D(z ) = Kd z¡zp z¡z0 0 z ¡z 0 p zp < z0 < 1, and 0 z0 < 0 zp < 1 are very close to 1. 18 ...
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This note was uploaded on 04/15/2011 for the course ECE 483 taught by Professor Evens during the Spring '08 term at Purdue University-West Lafayette.

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