115C_1_01a_ee_115c_outline

115C_1_01a_ee_115c_outline - – Finally due on Thursday,...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
EE115C Winter 2011 Digital Electronic Circuits KNSY PV Rm #1240B
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Personnel Instructor Sudhakar Pamarti 6731F Boelter Hall, (310) 825 2657, [email protected] Office Hours: TTh 10:00am 11:00am TA Abhishek Ghosh Reader TBD
Background image of page 2
3 Digital Integrated Circuits Basics Transistor behavior and fabrication technology Simple Static CMOS Logic Gate (Circuit) Design Delay, power analyses, transistor sizing, and layout Interconnect (Wires) R and C Combinatorial Logic Block Design Chain of logic gates Delay analysis, sizing; logical effort Sequential Logic Block Design Latches, flip-flops, timing analysis Design and simulation experience Cadence software, generic 90nm CMOS process
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Class Organization 6 homework assignments Due in class, see class web-site for schedule 1 design project Assigned in parts throughout the course
Background image of page 4
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 6
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: – Finally due on Thursday, March 10, 2011, in class Exams: midterm, final – Midterm: February 10, 2011, 8:00am – 9:50am – Final: Monday, March 14, 2011, 3:00pm – 6:00pm 5 Grading Policy Homework: 15% Project: 24% Midterm: 25% Final: 35% Survey: 1% No collaboration allowed unless explicitly specified 6 Class Material Textbook ( some slide material adapted from here ): Digital Integrated Circuits: A Design Perspective , by J. Rabaey, A. Chandrakasan, B. Nikolic, 2 nd Edition , (Prentice Hall 2003) Lab manuals – Available on the web-page Check web-page for the availability of tools http://www.eeweb.ee.ucla.edu (Go to > Online Lab) Or, go to http://www.ee.ucla.edu/~dejan/ee115c in your web-browser...
View Full Document

This note was uploaded on 04/16/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

Page1 / 6

115C_1_01a_ee_115c_outline - – Finally due on Thursday,...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online