115C_1_03a_ee_115c_cmos_inv

115C_1_03a_ee_115c_cmos_inv - EE115C Digital Electronic...

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EE115C Digital Electronic Circuits Lecture 3: Static CMOS Inverter
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2 Mapping Between Analog Signals and Digital Levels EE115C “ 0” V IL V IH V OH Undefined Region “ 1” V DD V OL GND Nominal Value Minimum Allowable Value Nominal Value Maximum Allowable Value Volts 0.5V DD
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3 Noise Margins EE115C Digital Ckt. #1 Digital Ckt. #2 V IL V IH V OH V DD V OL GND Volts 0.5V DD V IL V IH V OH V DD V OL GND Volts 0.5V DD Lowest Voltage Ckt. #2 still treats as “1” Highest Voltage Ckt. #2 still treats as “0” Noise Margin High, NM H =V OH – V IH Noise Margin High, NM L =V IL – V OL
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4 V in V out C L V DD Simplest Digital Electronic Circuit Inverter EE115C V in V out V DD GND Input 1 0 1 Output 0 1 0 ON, Triode OFF OFF ON, Triode
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5 V in V out C L V DD Inverter Voltage Transfer Characteristic (VTC) EE115C V in 0.2 0.4 0.6 0.8 1.0 NMOS res PMOS off NMOS sat PMOS sat NMOS off PMOS res NMOS sat PMOS res NMOS res PMOS sat 0.2 0.4 0.6 0.8 1.0 V out
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6 CMOS Inverter DC Load Curves I Dn V out V in = 2 V in = 1 V in = 0.8 V in = 0.6 V in = 0.4 V
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This note was uploaded on 04/16/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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115C_1_03a_ee_115c_cmos_inv - EE115C Digital Electronic...

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