115C_1_06_ee115c_cmos_gate_sizing

115C_1_06_ee115c_cmos_gate_sizing - EE115C Digital...

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EE115C Digital Electronic Circuits Lecture 6: CMOS Logic Gate Sizing
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EE115C 2 Transistor Sizing C L B R n A R p B R p A R n C int B R p A R p A R n B R n C L C int 2 2 2 2 1 1 4 4 Match worst cases to inverter pull-up and pull-down resistances
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3 OUT = D + A • (B + C) D A B C D A B C 1 2 2 2 4 4 8 8 Sizing of a Complex CMOS Gate: Example EE115C
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4 N Fan-out N Fan-in M M Fan-In and Fan-Out Definitions EE115C
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5 Fan-In Considerations D C B A D C B A C L C 3 C 2 C 1 Distributed RC model (Elmore delay) t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case. EE115C
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6 t p as a Function of Fan-In t p (ps) fan-in 0 250 500 750 1000 1250 2 4 6 8 10 12 14 16 quadratic linear t p t pLH t pHL NAND2 Gates with fan-in > 4 should be avoided EE115C
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7 t p as a Function of Fan-Out t p (norm.) eff. fan-out 2 4 6 8 10 12 14 16 t p NAND2 t p NOR2 t p INV 1 2 3 4 5 All gates have the same drive current Slope is a function of “driving strength” EE115C
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115C_1_06_ee115c_cmos_gate_sizing - EE115C Digital...

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