115C_1_8_ee115c_power [Compatibility Mode]

# 115C_1_8_ee115c_power [Compatibility Mode] - EE115C Digital...

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EE115C igital Electronic Circuits Digital Electronic Circuits Lecture 8: Power Consumption

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Power Consumption in CMOS Logic ± Dynamic Power Consumption Charging and discharging capacitors gg p ± Short Circuit Currents Simultaneous path from Vdd to Gnd through the pull-down and pull-up networks ± Leakage aking diodes and transistors Leaking diodes and transistors EE115C 2
Dynamic Power Dissipation ± Energy spent in charging / discharging capacitors V Vdd V Vdd in V out C L in V out C L nergy/transition = 2 nergy/transition = 2 Energy/transition = ½ C L V dd Energy/transition = ½ C L V dd 3 EE115C

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Node Transition Activity and Power Dissipation ± Consider switching a CMOS gate for N clock cycles of equency k frequency f clk E N = C L V dd 2 n ( N ) E : the energy consumed for N clock cycles N n ( N ): the number of 0 1 transitions in N clock cycles N n E ) ( clk dd L N clk N N avg f V C N f N P = = 2 lim lim ) N 01 () lim N nN N α →∞ ± 2 4 P avg = α 0 1 C L V dd f clk EE115C
Activity Factor Calculation (1/2) Example: Static 2-input NOR Gate AB O u t Assume signal probabilities p = 1/2 0 0 1 01 0 A =1 p B =1 = 1/2 hen

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## This note was uploaded on 04/16/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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115C_1_8_ee115c_power [Compatibility Mode] - EE115C Digital...

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