115C_1_10b_ee115c_dyn_logic

115C_1_10b_ee115c_dyn_logic - EE115C Digital Electronic...

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EE115C Digital Electronic Circuits Lecture 10b: Dynamic Logic
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EE115C 2 Dynamic Gate In 1 In 2 PDN In 3 M e M p CLK CLK Out C L Out CLK CLK A B C M p M e Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) on off 1 off on AB+C Out CLK A B C CLK
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3 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next pre-charge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L EE115C
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4 Properties of Dynamic Gates : Advantages Logic function is implemented by the PDN only number of transistors is N + 2 (vs. 2N for static CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (C out ) EE115C
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5 Overall power dissipation usually higher than static CMOS output node can float no glitching
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This note was uploaded on 04/16/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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115C_1_10b_ee115c_dyn_logic - EE115C Digital Electronic...

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