20111ee115C_1_hw1

20111ee115C_1_hw1 - EE 115C, Winter 2011, HW #1 (due...

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EE 115C, Winter 2011, HW #1 (due 1/18/2010) Problem 1: Using Cadence Spectre, generate the family of I-V curves for a PMOS transistor with the following parameters: W/L = 240nm/100nm Sweep V SD from 0V to 1V in 50mV increments Sweep V SG = 0.05, 0.1, 0.15, 0.2, 0.25, 0.3V, 0.35, 0.4, 0.7V, 1.0V V SB = 0V, 0.3V The online Tutorial #1 (from EEWeb > Online Laboratory) has detailed instructions on how to do this. Use the 90nm model as instructed in Tutorial 1, use section NN in the transistor model. (a) Plot the I SD vs V SG curves for V SD = 1.0V and both V SB values. Use linear x- and y- axes. (b) Repeat part (a) but use logarithmic y-axis. (c) Determine the approximate values of V T0 and V T from the curves you plotted in parts (a), (b). Assuming 2Φ F = –0.6V, calculate the value of the parameter γ. (d) Plot the I SD vs V SD curves for V SB = 0 and all swept values of V SG on one graph. Use linear x- and y- axes. (e) Repeat part (d) but use logarithmic y-axis.
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This note was uploaded on 04/16/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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20111ee115C_1_hw1 - EE 115C, Winter 2011, HW #1 (due...

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