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20111ee115C_1_hw2

# 20111ee115C_1_hw2 - EE 115C Winter 2011 HW#2(due Problem...

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EE 115C, Winter 2011, HW #2 (due 2/1/2011) Problem 1: (CMOS Gate Delay Calculations: Continuation of Problem #7 in Hw #1) Calcu- late the propagation delays from the input node to nodes X and Y in Figure 1 as they are being pulled up. Use the 90nm RC parameters posted on the class web-site. (10 points) Problem 2: CMOS Inverter Delay Calculation, Design, and Simulation (a) Calculate the t pLH , t pHL , and t P for a standard CMOS inverter with minimum length devices (L = 90nm) and NMOS width is 100nm and the PMOS width is 300nm. Use the resistance and ca- pacitance parameters tables posted on the class web- site in the “Handouts” section for your ca l- culations. Use V DD = 1.0 Volts. (b) Design the inverter i.e. chose the widths of the NMOS and PMOS transistors such that t p is a minimum. Calculate the t pLH , t pHL , and t p for the chosen size. (c) Perform a transient simulation on the inverter you designed in part (b) to determine t pLH , t pHL , and t p . For this simulation, drive the inverter with a 100MHz square wave with almost zero rise and fall times (use 0%-100% rise times and fall times of 1fs for simulation). See handouts posted

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20111ee115C_1_hw2 - EE 115C Winter 2011 HW#2(due Problem...

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