20111ee115C_1_hw3

20111ee115C_1_hw3 - EE 115C, Winter 2011, HW #3 (due...

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EE 115C, Winter 2011, HW #3 (due 2/8/2011) Problem 1: Multi-Gate Delay Analysis Using Logical Effort Calculate the delay at the output node, n4, of the chain of gates shown in Figure 1 corresponding to L H transition on node n1. Use logical effort principles and the tables on page 10 in the relevant lecture notes (Lecture #7: Sizing of Chain of Gates posted on the class web-site). For the above calculation assume also that node n3 is L when the transition occurs, and does not change before n2 has been pulled down. Use values from the “Simplified MOST switch model” handout posted on the class web-site for your calculations. For simplicity, as- sume that the widths of the transistors in the various gates are specified in the figure in μ m; all transistors have minimum lengths, 100nm. Assume that the pMOS transistor in G1 that is driven by node n1 is farthest from the gate’s output; the nMOS transistor in G2 that is driven by node n2 is farthest from the gate’s output. (20 points)
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This note was uploaded on 04/16/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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20111ee115C_1_hw3 - EE 115C, Winter 2011, HW #3 (due...

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