20111ee115C_1_hw4_hw5

20111ee115C_1_hw4_hw5 - EE 115C Winter 2011 HW#4_5(due...

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EE 115C, Winter 2011, HW #4_5 (due 3/1/2011) Problem 1: Pass Transistor Logic (12 points) Consider Figure 1. What are the steady state voltages (on the capacitors) for each of the follow- ing cases? Use V Tn = 0.3 and V Tp = –0.3, and ignore leakage currents. The initial voltages on the capacitors are shown. Problem 2: Pass Transistor Logic (8 + 4 + 6 = 18 points) Figure 3 is a logic gate implemented in the pass transistor logic style, with inputs, A and B, and output, Y. (a) What logic function does the gate realize? Please assume that R on (PMOS) >> R on (NMOS). (b) If the PMOS were removed, would the circuit still function correctly? (c) What purpose does the pMOS transistor serve? Problem 3: (Dynamic Logic) Please refer to a type of dynamic logic circuit shown in Figure 3(a). The signal CLK is a periodic square wave of time period T. a) Does the circuit evaluate during CLK = 1 or during CLK = 0? Explain. b)
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20111ee115C_1_hw4_hw5 - EE 115C Winter 2011 HW#4_5(due...

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