20111ee115C_1_hw6

20111ee115C_1_hw6 - EE 115C, Winter 2011, Hw #6 (due...

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EE 115C, Winter 2011, Hw #6 (due 3/10/2010) Problem 1: (Flip-Flop Timing) Consider the edge triggered flip-flop shown in Figure 1. Circuit simulations and measurements have revealed that it has a hold time, t H = 80ps. (a) Suggest modifications to the circuit that would decrease the hold time towards zero. You can add inverters (as many of them and wherever you want) in the flip-flop schematic. Assume that each inverter (irrespective of the loading conditions) add a delay of 30ps. (b) Does the set-up time of the flip-flop change as a result of your modifications? If t SU = 50ps before your modifications, how much would it be after your modifications? (10 + 10 = 20 points) Problem 2: (Clocking Methodology) Figure 2 shows a data path based on edge-triggered flip- flops. Both clock signals, Φ α and Φ β , have the same frequency but potentially have a skew be- tween them. Suppose that t c-q = 0.4 ns, t su = 0.7 ns, t hold = –0.3 ns. The maximum and minimum propagation delays of the combinational logic for any path are shown (in ns) on the figure. (a)
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This note was uploaded on 04/16/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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20111ee115C_1_hw6 - EE 115C, Winter 2011, Hw #6 (due...

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