module booth2

module booth2 - 2'b10 : pp4 = {a_ext_neg[4:0], 3'b000};...

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module booth2 (a, b, rslt); input [3:0] a, b; output [7:0] rslt; wire [3:0] a, b; wire [7:0] rslt; wire [3:0] a_bar; wire [7:0] a_ext_pos; wire [7:0] a_ext_neg; reg [3:0] a_neg; reg [7:0] pp1, pp2, pp3, pp4; //test b[1:0] assign a_bar = ~a; always @ (a_bar) a_neg = a_bar + 1; assign a_ext_pos = {{4{a[3]}}, a}; assign a_ext_neg = {{4{a_neg[3]}}, a_neg}; always @ (b, a_ext_neg) begin case (b[1:0]) 2'b00 : begin pp1 = 8'h00;
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pp2 = 8'h00; end 2'b01 : begin pp1 = a_ext_neg; pp2 = {{3{a[3]}}, a[3:0], 1'b0}; end 2'b10 : begin pp1 = 8'h00; pp2 = {a_ext_neg[6:0], 1'b0}; end 2'b11 : begin pp1 = a_ext_neg; pp2 = 8'h00; end endcase end //test [2:1] always @ (b, a_ext_pos, a_ext_neg)
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begin case (b[2:1]) 2'b00 : pp3 = 8'h00; 2'b01 : pp3 = {a_ext_pos[5:0], 2'b0}; 2'b10 : pp3 = {a_ext_neg[5:0], 2'b00}; 2'b11 : pp3 = 8'h00; endcase end //test b[3:2] always @ (b, a_ext_pos, a_ext_neg) begin case (b[3:2]) 2'b00 : pp4 = 8'h00; 2'b01 : pp4 = {a_ext_pos[4:0], 3'b000};
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Unformatted text preview: 2'b10 : pp4 = {a_ext_neg[4:0], 3'b000}; 2'b11 : pp4 = 8'h00; endcase end assign rslt = pp1 + pp2 + pp3 + pp4; endmodule //test bench module booth2_tb; reg [3:0] a, b; wire [7:0] rslt; initial $monitor ("a = %b, b = %b, rslt = %h", a , b, rslt); initial begin //test b[1:0] #0 a = 4'b0111; b = 4'b1000; #10 a = 4'b0110; b = 4'b0101; #10 a = 4'b1110; b = 4'b0110; #10 a = 4'b1011; b = 4'b1011; // test b[2:1] #10 a = 4'b0001; b = 4'b1000; #10 a = 4'b0111; b = 4'b1011; #10 a = 4'b1011; b = 4'b1100; #10 a = 4'b0111; b = 4'b0111; // test b[3:2] #10 a = 4'b0111; b = 4'b0000; #10 a = 4'b1111; b = 4'b0101; #10 a = 4'b0101; b = 4'b1010; #10 a = 4'b1101; b = 4'b1100; #10 $stop; end // instantiate the module into the test bench booth2 inst1 ( .a(a), .b(b), .rslt (rslt) ); endmodule...
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module booth2 - 2'b10 : pp4 = {a_ext_neg[4:0], 3'b000};...

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