270F09exam1review

# 270F09exam1review - EECS 270 in-class Exam Review 1 Using...

This preview shows pages 1–3. Sign up to view the full content.

EECS 270 in-class Exam Review 1. Using no more than five 2-input NAND gates and nothing else, design an XOR gate. You may freely use “0” and “1” as inputs. [5] 2. Convert the values as indicated: [5 points, -1 per wrong or blank answer] a) 23 10 into 7-bit 2’s complement ____________ b) -3 10 into 4-bit 2’s complement ____________ c) 10001 from 5-bit 2’s complement to decimal ____________ d) -1 10 into 4-bit 2’s complement ____________ e) -4 10 into 5-bit signed-magnitude ____________ f) 7.125 10 into base 4 ____________ 1/6

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
3. Consider the following circuit where every gate has a delay of 5 ns except the XOR which has a delay of 10ns. a) If A is held at 0 and D is held at 1, what is the longest delay between changes that could occur due to changes in B and C and when Q changes? List the path (by letters of the output) that delay occurs on. [4] b) If B is held at 1 and C is held at 0, what is the longest delay between changes that could occur due to changes in A and D and when Q changes? List the path (by
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 04/18/2011 for the course EECS 270 taught by Professor David during the Spring '11 term at Michigan State University.

### Page1 / 6

270F09exam1review - EECS 270 in-class Exam Review 1 Using...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online