EECS 270 inclass
Exam Review
1.
Using no more than five 2input NAND gates and nothing else, design an XOR gate.
You may freely use “0” and “1” as inputs.
[5]
2.
Convert the values as indicated:
[5 points, 1 per wrong or blank answer]
a)
23
10
into 7bit 2’s complement
____________
b)
3
10
into 4bit 2’s complement
____________
c)
10001 from 5bit 2’s complement to decimal
____________
d)
1
10
into 4bit 2’s complement
____________
e)
4
10
into 5bit signedmagnitude
____________
f)
7.125
10
into base 4
____________
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View Full Document3.
Consider the following circuit where every gate has a delay of 5 ns except the XOR
which has a delay of 10ns.
a)
If A is held at 0 and D is held at 1, what is the longest delay between changes that
could occur due to changes in B and C and when Q changes?
List the path (by
letters of the output) that delay occurs on.
[4]
b)
If B is held at 1 and C is held at 0, what is the longest delay between changes that
could occur due to changes in A and D and when Q changes?
List the path (by
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 Spring '11
 david
 Gate, Logic gate, 4bit, 7bit, 3bit, 5bit, 6 bits

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