270L03Notes - 0 EECS 270 Fall 2009 Lecture 3 Page 1 0 1 of...

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O 0 I 0 O 1 I 1 O 2 O 3 2 to 4 decoder I 0 I 1 O 0 I 2 O 1 I 3 4 to 2 encoder 0 1 2 3 A S[1:0] X B C D 2 0 1 A[3:0] S B[3:0] X[3:0] 8 to 4 MUX 4 4 4 4 to 1 MUX x y z EECS 270, Fall 2009, Lecture 3 Page 1 of 7 I. Medium Scale Integrated (MSI) devices [Sections 2.9 and 2.10] As we’ve seen, it’s sometimes not reasonable to do all the design work at the gate-level. For example, we used full-adders as the building blocks of our ripple-carry adder. You can imagine that as we do designs we might find that there are certain building blocks we use over and over again. As you might imagine, being familiar with a set of building blocks that are commonly used can make designing digital devices easier. Building blocks that are more complex than gates, are sometimes called medium-scale integrated devices, or MSI devices for short. Exactly what makes a device “medium” in scale rather than “large” or “very large” (VLSI) is not always agreed on, but we’ll generally stick with devices that are fairly simple and where small versions of them can be implemented in a couple dozen gates or less. The devices We’ll cover four common devices today: decoder, encoder, priority encoder and MUX. The MUX we’ve seen before. Other MSI devices you should be familiar with are the comparator and deMUX. Decoder o N inputs, 2 N outputs. o
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This note was uploaded on 04/18/2011 for the course EECS 270 taught by Professor David during the Spring '11 term at Michigan State University.

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270L03Notes - 0 EECS 270 Fall 2009 Lecture 3 Page 1 0 1 of...

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