270L07Notes - EECS 270 Fall 2009 Lecture 7 Page 1 of 3 EECS...

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Unformatted text preview: EECS 270, Fall 2009, Lecture 7 Page 1 of 3 EECS 270 Fall 2009 Lecture 7 (9/30/09) Use pencil! Lecture 6 Recap • • • • • Combinational vs. sequential circuits VTC: Voltage Transfer Curve (or Characteristic) of digital gates Bistable: single‐bit memory using feedback Metastability! SR (Set‐Reset) latch • Hold (maintain stored value): S=R=0 • Set (write "1"): S=1, R=0 • Reset (write "0"): S=0, R=1 • Invalid combination: S=R=1 D (Data or Delay) latch • Set: D=1 • Reset: D=0 • Today • Functional classification of storage elements • Next‐State (or Characteristic) Table/Equation: next‐state = f(present‐input, present‐state) • Excitation (or Required Input) Table/Equation: input = f(present‐state, next‐state) • Types: SR, D, T, JK Temporal classification of storage elements • Clocked vs. unclocked • Clocked: • Level‐ Sensitive • Edge‐Triggered Timing contsraints to avoid metastability • Setup time • Hold time • Input‐to‐output propgation delay • • EECS 270, Fall 2009, Lecture 7 Page 2 of 3 Level­Sensitive D Latch D Latch "door" SR Latch S C R QB Q C D S R Q QB D C Q Q EECS 270, Fall 2009, Lecture 7 Page 3 of 3 Edge­Triggered D Flip­Flop D D C Q Q M D C Q Q Q C C D M Q D C Q Q ...
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  • Spring '11
  • david
  • Gate, Volt, sr latch, voltage transfer curve, Input‐to‐output propgation delay, JK  Temporal classification, Edge‐Triggered  Timing contsraints, Level­Sensitive D Latch

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