270L12-Timing+Issues - Timing Issues Delay Setup and hold...

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1 1 UM EECS 270 Fall 2009 Timing Issues • Delay • Setup and hold times • Determining clock frequency/period • Synchronizing external (asynchronous) inputs • Initializing flip-flops • Clock skew • Glitches • Timing analysis 2 Min & Max Input-to-Output Delays EN Q 0 Q 1 D 0 D 1 01 0 1 DD EN Q Q Min Delays 0 1 EN Q Q Max Delays NAND delay = 2ns INV delay = 1ns
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2 3 UM EECS 270 Fall 2009 Setup and Hold Times • To set, S must be held at 1 for at least 2 NOR delays •S = D * C • D must change to 1 at least 2 NOR delays before C goes to 0 (closes the latch) S R D C QB Q SR Latch Latch "door" Positive Level-Sensitive D Latch 4 Setup and Hold Times • By insuring that the D input is stable for a specified minimum length of time before (setup) and after (hold) the appropriate clock edge we eliminate metastability! • Assume that setup and hold times are provided. They can be calculated, but the analysis is tricky. • Which clock edge? C D Q Q C D Q Q C D Q Q C D Q Q
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3 5 UM EECS 270 Fall 2009 Determining Minimum Clock Period 01 0 1 DD EN Q Q Min Delays 0 1 EN Q Q Max Delays Clock-to-Q delay = 4ns Setup time = 4ns Hold time = 2ns 6 Asynchronous inputs* • Not all inputs are synchronized with the clock • Examples: – Keystrokes – Sensor inputs – Data received from a network (transmitter has its own clock) • Inputs must be synchronized with the
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270L12-Timing+Issues - Timing Issues Delay Setup and hold...

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