{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

270L12-Timing+Issues - Timing Issues Delay Setup and hold...

Info icon This preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
1 1 UM EECS 270 Fall 2009 Timing Issues • Delay Setup and hold times Determining clock frequency/period Synchronizing external (asynchronous) inputs Initializing flip-flops Clock skew • Glitches Timing analysis 2 UM EECS 270 Fall 2009 Min & Max Input-to-Output Delays EN Q 0 Q 1 D 0 D 1 0 1 0 1 D D EN Q Q Min Delays 0 1 0 1 D D EN Q Q Max Delays NAND delay = 2ns INV delay = 1ns
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 3 UM EECS 270 Fall 2009 Setup and Hold Times To set, S must be held at 1 for at least 2 NOR delays S = D * C D must change to 1 at least 2 NOR delays before C goes to 0 (closes the latch) S R D C QB Q SR Latch Latch "door" Positive Level-Sensitive D Latch 4 UM EECS 270 Fall 2009 Setup and Hold Times By insuring that the D input is stable for a specified minimum length of time before (setup) and after (hold) the appropriate clock edge we eliminate metastability! Assume that setup and hold times are provided. They can be calculated, but the analysis is tricky. Which clock edge? C D Q Q C D Q Q C D Q Q C D Q Q
Image of page 2