270L15Notes - EECS 270 Fall 2009 Lecture 15 Controller Class status e M etastability(from wikicommons Datapath Homework 5 due at 2pm today Lab

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Controller Datapath EECS 270, Fall 2009, Lecture 15 Page 1 of 11 Class status Homework 5 due at 2pm today Lab 5 (inlab/postlab) due this week. Lab 6 posted. o It’s a variation of Group Assignment #2, though a bit more complex and you need to convert to Verilog. o We think the prelab should only take 2-3 hours, but the inlab might be quite a bit longer (new lab, we aren’t sure!) . So we strongly recommend getting going on the Verilog ASAP. I. Review Let’s quickly go over what we’ve done in the last few weeks. Timing issues Define the following terms: Setup time:________________________________________________________________________ Hold time: _________________________________________________________________________ Clock to Q: (term not covered in class): __________________________________________________ Metastability: ______________________________________________________________________ What causes metastability?:__________________________________ Fundamentally, in digital design we are assuming that we pick our clock period (and deal with hold time issues) so that metastability won’t happen. That said, sometimes we can’t just design our way out of the problem. When does that happen?
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This note was uploaded on 04/18/2011 for the course EECS 270 taught by Professor David during the Spring '11 term at Michigan State University.

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270L15Notes - EECS 270 Fall 2009 Lecture 15 Controller Class status e M etastability(from wikicommons Datapath Homework 5 due at 2pm today Lab

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