270L18Notes - EECS 270, Fall 2009, Lecture 18 Page 1 of 14...

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A[9:0] OE Data[7:0] WE Clock 10 8 EECS 270, Fall 2009, Lecture 18 Page 1 of 14 I. Memories (5.6) A memory is a device that acts like a big array. You supply an index (called an address) and it supplies the data at that location. You can also write to a given address. On the left is a 1024x8 memory. That is it has 1024 entries and each entry is 8 bits wide. If Write Enable (WE) is a 1, that means we want to write the value on the data lines into the memory location specified by the address (A) lines. If WE is a 0 and Output Enable (OE) is a 1 that means we want the data at location A to be put on the Data lines. If both WE and OE are zeros, Data is high-Z. Notice that data is sometimes an input and sometimes an output! Questions: 1. What values should we apply if we want to write 0x12 to memory location 0x044? A[9:0]= __________ OE=______ WE=______ Data[7:0]=__________ 2. What values should we apply if we want to read memory location 0x44? A[9:0]= __________ OE=______ WE=______ Data[7:0]=__________ Types of memories There are a number of different types of memories each with a different set of properties . ROM:___________________________________________________________________________ RAM:___________________________________________________________________________ Volatile vs. Non-volatile: ___________________________________________________________ Static vs. Dynamic:_________________________________________________________________ And we commonly find the following common memory types: DRAM: ___________________________________________________________________________ SRAM: ____________________________________________________________________________ Flash*: _____________________________________________________________________________
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EECS 270, Fall 2009, Lecture 18 Page 2 of 14 *Note that flash is a particular technology. There are other things like Magnetoresistive RAM (MRAM) that has similar properties. Inside the memories—the little picture Memories are generally large arrays with small 1-bit cells in them. Let’s look at the cell in an SRAM i and DRAM ii . On the left is a single SRAM cell. The inverter pair should be familiar to you—it’s the same bi-stable device we started with as a starting point for a latch. The other devices are transistors. We’ll cover them in a few weeks, but in this context you can basically think of them as being a door. If the word line is high, A connects to Q and B connects to Qbar. Otherwise they don’t. To read from the device, we simply set the word line high and read the bit line. To write, we “strongly” drive the bit lines and set the word line to be one. That will override the inverter pair’s relatively weak signal. DRAM works in a very similar way. The main difference is that a capacitor is used to store the value. That capacitor will only hold the value for a short time (on the order of 1 to 10 ms!). (A capacitor is a device that holds a certain voltage level for a while). It also suffers from a feature called a “destructive read”—when you read the data, the data is lost.
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270L18Notes - EECS 270, Fall 2009, Lecture 18 Page 1 of 14...

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