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270L19-Two+Level+Logic+Minimization

270L19-Two+Level+Logic+Minimization - Logic Synthesis From...

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1 UM EECS 270 Fall 2009 Logic Synthesis: From Specs to Circuits Implementation Styles – Random – Regular Optimization Criteria Area (roughly number of transistors) Delay (roughly number of gates on longest circuit path) – Testability Power consumption 2-Level Synthesis Classical (Exact) Heuristic (Non-Exact) Multilevel Synthesis UM EECS 270 Fall 2009 Logic Expressions Ù Circuits f stv stwx styz uv uwx uyz = + + + + + ( )( ) f st u wx yz v = + + +
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2 UM EECS 270 Fall 2009 2-Level Circuits Assumptions: Inputs are available in both true and complemented forms (reasonable assumption: FF outputs are available in both phases) Gates have no fan-in or fan-out restrictions (unreasonable assumption: typically FI < 4, FO < 6) Correspond to SOP or POS forms of a switching function: – SOP Ù AND/OR (NAND/NAND) – POS Ù OR/AND (NOR/NOR) # of 1st level AND (OR) gates = # of nontrivial product (sum) terms Fan-in of 2nd level OR (AND) gate = total # of product (sum) terms Usually implemented using regular structures: Read-Only Memories (ROMs) Programmable Logic Arrays (PLAs) UM EECS 270 Fall 2009 AND/OR Ù NAND/NAND
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