lecture15 - 2N 2N 2N 2N X Y Z 0 Hold 1 Load 2 Shift Right 3...

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Lecture 15 slides EECS 270, Fall 2009
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Registers
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State Machine (Controller) Data Path X, Y, Z Zero A[N-1:0] B[N-1:0] Out[2N-1:0] Go Done Multiplier
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RS: 2N-bit register RB: N-bit register 0 1 N{0} A[N-1:0] B[3:0] N N N 2N 2N{0} 8-bit Adder RA: 2N-bit register Shift Registers shift A 0 into the “open” spot. Out[2N-1:0] Bob
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Unformatted text preview: 2N 2N 2N 2N X Y Z 0 Hold 1 Load 2 Shift Right 3 Shift Left RB[0] RB=zero? zero Waiting X= Y= Z= Done= G is Go Z is Zero _______ X= Y= Z= Done= _______ X= Y= Z= Done= _______ X= Y= Z= Done= _______ X= Y= Z= Done= CLK Go X Y Z Bob RA RB RS...
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lecture15 - 2N 2N 2N 2N X Y Z 0 Hold 1 Load 2 Shift Right 3...

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