lecture16 - ago. • Gates, truth tables, MSI devices, etc....

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
State Machine Data Path X, Y, Z Zero A[3:0] B[3:0] Out[7:0] Go Done 4-bit Multiplier
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
RS: 8-bit register RB: 4-bit register 0 1 0000 A[3:0] B[3:0] 4 4 4 8 0000000 8-bit Adder RA: 8-bit register Shift Registers shift A 0 into the “open” spot. Out[7:0] Bob 8 8 8 8 X Y Z For RA and RB 0 Hold 1 Load 2 Shift Right 3 Shift Left RB[0] RB=zero? zero For RS 0 Load 1 Clear 2 Hold 3 Shift Left
Background image of page 2
Waiting X= Y= Z= Done= G is Go Z is Zero _______ X= Y= Z= Done= _______ X= Y= Z= Done= _______ X= Y= Z= Done= _______ X= Y= Z= Done=
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CLK Start X Y Z Bob RA RB RS
Background image of page 4
CLK Start X Y Z Bob RA RB RS
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Taking stock Where are we? We finished combinational logic design a few weeks
Background image of page 6
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 8
Background image of page 9
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ago. • Gates, truth tables, MSI devices, etc. – We’ve almost finished sequential logic design. • Flip-flops, registers, state machine design etc. • Some to do: – Mealy vs. Moore – Memories • Next up is optimization – How do we simplify combinational logic? – How do we reduce the number of states? Let’s finish up the rest… • We’ll probably need most/all of next Monday too. Mealy vs. Moore “11” Mealy vs. Moore “11”...
View Full Document

This note was uploaded on 04/18/2011 for the course EECS 270 taught by Professor David during the Spring '11 term at Michigan State University.

Page1 / 9

lecture16 - ago. • Gates, truth tables, MSI devices, etc....

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online