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Unformatted text preview: Name:___ MASTER _____________ CMIS 310 Spring 2011 ONLINE ASSIGNMENT #4 - Module 4 This assignment consists of eight questions worth a total of 106 points. The assignment is worth 10% of your course grade. 1. (21 points) Consider a CPU that implements four parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the commentary, i.e.: a one clock cycle fetch a one clock cycle decode a two clock cycle execute and an 60-instruction sequence For a 60-instruction sequence: no pipelining would require: 60 instructions x 4 clock cycles/instruction = 240 clock cycles a scalar pipeline would require: 4 clock cycles for the first instruction, plus one additional clock cycle for each of the other fifty-nine instructions: 4 clock cycles + (59 instructions x 1 clock cycle/instruction) = 63 clock cycles a superscalar pipeline with four parallel units would require: 4 cycles for the first set of four instructions, plus one additional clock cycle for each of the other fourteen 4-instruction sets: 4 clock cycles + (14 instructions x 1 clock cycle/instruction) = 18 clock cycles 1 2. (30 points) Show the layout of the specified cache for a CPU that can address 512M x 64 of memory. Give the layout of the bits per location and the total number of locations. . a) The cache holds 1M x 64 of data and has the fully associative strategy 512M = 2 29 ; therefore the tag is 29 bits 29 bit tag 64 bits data Valid bit There are a total of 94 bits in each location and a total of 1M locations (also known as cache words) b) The cache holds 1M x 64 of data and has the direct mapped strategy 512M = 2 29 in memory)/(1M = 2...
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This note was uploaded on 04/23/2011 for the course CMIS 310 taught by Professor Daumit during the Spring '11 term at Cornell University (Engineering School).
- Spring '11