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4FE324BEd01 - d Design an 8-to-1 multiplexer(mux e Using...

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1 EE 347 – Computer Logic Design Prof. Warter-Perez Homework 1 Due Wednesday 1/24/2011 1. Design a register file with 8 4-bit registers, two read ports, and one write port. a. Show the block diagram of the register file labeling all inputs, outputs, bits per bundled wire, and the block. b. Design a 4-bit parallel load register using 2-to-1 muxes and positive edge triggered flip-flops. c. Design a 3-to-8 decoder with enable.
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Unformatted text preview: d. Design an 8-to-1 multiplexer (mux). e. Using block diagrams for the 4-bit register, the 3-to-8 decoder, and the 4-to-1 mux, design the register file on paper. For one read port, show individual multiplexers (one per bit). For the other read port, use arrayed multiplexers (the data inputs and output are 4-bit values). f. Describe how you would modify your design so that register 0 is always 0....
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