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EE 347 – Computer Logic Design
Homework #3
Due Monday, February 14
th
at the beginning of class
Note: the designs for this homework assignment are all paper designs, i.e., no Verilog.
1.
Design a full adder using logic gates. You can either do sum of minterms or
optimize your design using Karnaugh Maps.
2.
Design a 3bit ALU that can perform the following operations:
add, subtract,
xor,
and
sge
(set greater than or equal which is the inverse of slt).
a.
Draw the operation table. List the operation bits (op) on the left side and
the operation on the right side.
b.
Design a 1bit ALU that can be used for bit 0 and bit 1 of your ALU.
c.
Design a 1bit ALU that can be used for the most significant bit (bit 2) of
your ALU. This ALU should have the same hardware as the one from
step b but also provide the
set
output for
sge
and compute
overflow
.
d.
Show the design of the 3bit ALU connecting two of the ALUs from step
b and one ALU from step c together. Add the necessary hardware to
compute a zero output (zero = 1 when the result is zero (000)).
e.
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This document was uploaded on 04/24/2011.
 Spring '09
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