EE 347 Homework 3 Solution (Winter 2011)

EE 347 Homework 3 Solution (Winter 2011) - EE 347 Computer...

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1 EE 347 – Computer Logic Design Homework #3 - Solution Note: the designs for this homework assignment are all paper designs, i.e., no Verilog. 1. Design a full adder using logic gates. You can either do sum of minterms or optimize your design using Karnaugh Maps.
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2 2. Design a 3-bit ALU that can perform the following operations: add, subtract, xor, and sge (set greater than or equal which is the inverse of slt). a. Draw the operation table. List the operation bits (op) on the left side and the operation on the right side. b. Design a 1-bit ALU that can be used for bit 0 and bit 1 of your ALU.
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3 c. Design a 1-bit ALU that can be used for the most significant bit (bit 2) of your ALU. This ALU should have the same hardware as the one from step b but also provide the set output for sge and compute overflow . d. Show the design of the 3-bit ALU connecting two of the ALUs from step b and one ALU from step c together. Add the necessary hardware to compute a zero output (zero = 1 when the result is zero (000)).
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4 e. Show the block diagram of the 3-bit ALU. Use the standard symbol for an ALU and make sure to label all inputs and outputs and specify how many bits per input/output. f. List sample test inputs (a, b, and op) and outputs (r, cout, overflow, and zero) for your 3-bit ALU for the following cases: i. add with cout = 1 (in other words, the inputs used will cause cout to be 1 after the add is performed) a b op r cout overflow zero 111 001 01 000 1 0 1 Note, 111 + 001 is either 7 + 1 = 8 (unsigned) which is out of range (cout = 1) or 111 + 001 is -1 + 1 = 0 (signed) which is in range (overflow = 0). Note, since the 3-bit result is 000, the zero output is 1. ii. add with overflow = 0 and cout = 0 a b op r cout overflow zero 001 010 01 011 0 0 0 001 + 010 = 011 (both signed and unsigned) and is in range (1 + 2 = 3) for both so both cout and overflow are 0. Zero is 0 since the result (r) is not zero (it is 011).
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