SP10-pp2-sol

SP10-pp2-sol - UNIVERSITY OF CALIFORNIA—DAVIS DEPARTMENT...

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Unformatted text preview: UNIVERSITY OF CALIFORNIA—DAVIS DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING EEClSOA—DIGITAL SYSTEMS I Spring 2010 SOLUTIONS OF PRACTICE PROBLEMS — SET 2 1. NUMBER REPRESENTATION O D) O L) L) l—‘l—‘l—‘l—‘OOOOOOO ll I I l—‘l—‘l—‘l—‘OOOl—‘l—‘l—‘l—‘OOO l—‘l—‘UUl—‘l—‘Ul—‘l—‘UUl—‘l—‘U Ul—‘Ul—‘Ul—‘Ul—‘l—‘Ul—‘Ul—‘UH O O L) F_I— Gull Using the Karnaugh maps below, we can get the following equations: Y3 = X3X2+X3X1+X3X0 = X3(X2X1X0) Y2 = X2X3 +X2X1 +X2X0 +X3X2X1X0 = X2(X3X1X0) +X3X2X1X0 = X2 O (X3X1X0) Y1 = X1X3 +X1X0 +X3X1X0 = X1(X3X0) +X3X1X0 = X1 93 (X3X0) Y0 = XOX3 +X3XO 2 X3 (-BXO 1 HussamAz-Asaad 2. ALU DESIGN The aim of this problem is to design a bit slice of the ALU shown below. The ALU performs one of the eight operations (summarized in the table below) on the two data inputs A = A” ,1...A0 and B = B”, 1...B0 according to the values of the selection input S = SZSISO. S2 S1 S0 ALU Operation 0 0 0 Fi=0 0 0 1 Fi=BminusA 0 l 0 Fi=AminusB 0 l 1 Fi=AplusB l 0 0 Fi=AXORB l 0 l Fi=AORB l l 0 Fi=AANDB 1 1 1 Fi=l The block diagram of slice 1' is shown above. There are two outputs for each slice. For slice 1', the outputs are Fi and Ci + 1. We can rewrite the function table above for slice 1' as shown below. For the case ofA plus B, we have: FizAiEIrDBiEBCl. CH1 =AiBi+(Al.€BBl.)Cl. For the case ofB minus A, we have: B i A = B + (7A). In order to achieve this result, we need to get the 2’s com- plement ofA and add it to B. This can be done by inverting the Al- bits and adding 1 to the result. Adding l to the result is equivalent to setting C0 = 1. Therefore, we have: FizAiEIrDBiEBCl. CH1 =AiBi+(Al.€BBl.)Cl. C0=1 The rest of the table can be determined in a similar way. Based on the table above, we can determine the equations of F 1-, C,- + 1, and C0. Fl. = szslsom) + szslsowl. (a 31.93 Cl.) + 525150011. a) Bl. a) C1.) + szslsowl. (a Bl. a) C1.) + 2 HussamAz-Asaad S2 S1 Outputs of slice 1' 0 0 . CH] 2 don't care 0 0 . . ._ EB. (Z0390. l l l l l l 0 l ._ .B. (A.OBZ.)CZ. l 0 1 ._ l. 1. (4.0399. l 0 ._ don't care don ’t care 1 0 . . . ._ don't care don ’t care 1 1 . l. l. ._ don't care don’tcare l l . ._ don't care don ’t care stlsoml. @ Bl.) + stlsoml. —— Bl.) + SZSISOMZBZ.) + 325130( 1) CH1 2 SZ[SISO(AI.BI.+ (Al. 6-) Bl.)Cl.) ——SISO(Al.Bl.+ (Al. 6-) Bl.)Cl.) + SISO(Al.Bl.+ (Al. 6-) Bl.)Cl.)] C0 2 5150 The above equations can be easily implemented using logic gates. They can be minimized to simplify the overall logic. 3. WAVEFORMS Complete the output waveform of (a) positive-edge triggered JK flipflop, and (b) negative-edge triggered JK flip- flop. I—II—II—Il—II—I—I —l|—l|—l|—l|—ll—|_ Clk Km (3) (b) Hussain Al-Asaad U) 4. WAVEFORMS Complete the timing diagram for the circuit below. Assume that the initial values of the flip-flops is 0. Moreover, assume that the delay of flip-flops and gates is negligible. X A I) Fliptflop /\ Z I) FI' - I 1P f or) B C Ik Clk 5. FLIP-FLOP DESIGN Design a D flip-flop that operates on both the positive and negative edges of the clock. Hint: Use a positive edge D flip-flop, negative edge D flip-flop, and a 2-to-1 multiplexer. I) Him/lop /\ DF/Ifltflofl Clk 4 HussamAz-Asaad 6. SINGLE-SEQUENCE COUNTER DESIGN Design a counter that count in the following sequence: 0, 2, 7, 4, 6, 3, l, 0, Toggle Wm“ Q1 T2 T1 T0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 0 l O l X X X X X X 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 0 1 1 T2=Q1Q0 T12Q1Q0+Q1Q02Q1®Q0 Q2Q1 Q2Q1 T0 = Q1Q0+Q1Qo+ or = [email protected]+ or Qon Qon Resulting State Diagram Clk The counter is self-starting— if the counter starts in the invalid state 101, it will go to the correct counting sequence after one clock. 5 HussamAz-Asaad 7. MULTI-SEQUENCE COUNTER DESIGN A particular 2-bit counter counts in binary (00, 01, 10, 11, 00, ...) if the input M = 0 and counts in gray code (00, 01, 11, 10, 00, ...) if the input M = 1. In addition to the state outputs, the counter has an output Z which is set to 1 if the counter is in state 11. Design the counter using JK-flipflops. OHXXHOXX t—‘><O><t—‘><t—‘>< JIZQO K1 2 ZT/[QO+MQ—0 = Me) Q0 JO 2 M+Q1= MQ1 K0 2 M+Q1 Z = QIQO T-F/ipflop Q1 Q0 T-F/ipflop Clk 6 Hussain Al-Asaad 8. COUNTER ANALYSIS The equations for the toggle inputs can be determined from the figure as: TA=A+B®C; TB=A+B;and TC=A+B®C We can complete the state transition table as follows: Current State Toggle inputs Next state 0 ® ® Resulting State Diagram 9. JOHNSON COUNTER The 4-bit Johnson counter advances through the sequence 0000, 1000, l 100, ll 10, 111 l, 01 l l, 0011, 0001, and repeats. Using the standard counter design procedure, implement the 4-bit Johnson counter using (a) D-flipflops and (b) T-flipflops. Current State Next State inputs of D flip-flops inputs of T flip-flops Q3 Q2 Q1 Q0 t—‘t—‘t—‘t—‘t—‘t—‘t—‘t—‘OOOOOOO- D—‘D—‘D—‘D—‘OOOOD—‘D—‘D—‘D—‘ooo- D—‘D—‘OOD—‘D—‘OOD—‘D—‘OOD—‘D—‘o- t—‘Ot—‘Ot—‘Ot—‘Ot—‘Ot—‘Ot—‘Ot—‘O -><~><><><~o><><><o><o- HHXHXXXOHXXXOXO- HHXOXXXOHXXXHXO- HHXHXXXHOXXXOXO- wawxxxowxxxoxo- HHXOXXXOHXXXHXO- ooxo><><><-><><><o><oc OO><~><><><OO><><><H><OO OHXOXXXOOXXXOXH- 0 X 0 X X X 0 l X X X l X l 0 wawxxxwoxxxoxo ~O><O><><><OO><><><O><O By using Karnaugh Maps, we get the following equations: D3ZQ0’D22Q3’D12Q2’D02Q1 T3 = Q—3Q—0+Q3Q0 = Q3®Q0 7 HussamAz-Asaad T2 2 Q—3Q2“Q3Q—2 Z Q39Q2 T1: Q—2Q1“Q2Q—1 Z QzeQi To Z Q—iQo“Q1Q—0 Z Qier So, we can implement the Johnson counters as shown below: 10.COUNTER DESIGN Using JK flip-flops, design a counter that counts in the following sequence: 000, 111, 001, 110, 010, 101, and repeat. Draw the schematic of your final design. Check whether your counter is self-starting or not. Current State Next State inputs OfJKflip-flops Q2 Q1 Q0 Q2+ QC Q0+ J2 K2 J1 K1 J0 K0 >—‘>—‘>—‘>—‘OOO t—‘t—‘OOt—‘t—‘O t—‘Ot—‘Ot—‘Ot— OOOXxl—‘H ol—‘OXXOD—t t—OOXxl—‘O ><><><><><HH -~><><><><>< ><><O><><><~ t—O><><><l—‘><>< ><O><><><~>< OXl—‘XXXl—‘X By using Karnaugh Maps, we get the following equations: J2 2 K2 2 1 , J1 = J = Q—2 , K0 2 Q—1 , and K1 2 Q—2 + Q0 . The counter schematic is thus as shown below. 8 Hussain Al-Asaad JKflifltflofl To check if the counter is self-starting, we need to determine the next states for the states that are not part of the counting sequence. Current State inputs of JK‘ fl ip-flops Next State The complete state diagram is thus as follows: It is clear from the above state diagram that the counter is self-starting. Hussain Al-Asaad 1 1 . COUNTER ANALYSIS Draw the state diagram of the counter shown below. Qo So ROAE Clock From the circuit, we can get the following equations: J1 = Q0 , K1 2 Q1 69 Q0 , S0 = Q—1 , and R0 = QIQ0 . Now, let us compute the next state equations using the characteristic equations ofthe flip-flops: + _ _ _ — Q] 2 J1Q1+K1Q1: Q0Q1+(Q1®Q0)Q1: Q0 Jr _ _ — _ Q0 2 So+R0Q0 = Q1 +(Q1Q0)Q0 = Q1 So, the state transition table and the state diagram are as follows: Current State Next State In fact, the above circuit is a 2-bit gray code counter. 10 Hussain Al-Asaad ...
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This note was uploaded on 04/25/2011 for the course EEC 180A taught by Professor Redinbo during the Spring '08 term at UC Davis.

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SP10-pp2-sol - UNIVERSITY OF CALIFORNIA—DAVIS DEPARTMENT...

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