SP10-pp3-sol

SP10-pp3-sol - UNIVERSITY OF CALIFORNIADAVIS DEPARTMENT OF...

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UC Davis 1 Hussain Al-Asaad U NIVERSITY OF C ALIFORNIA —D AVIS D EPARTMENT OF E LECTRICAL & C OMPUTER E NGINEERING EEC180A—D IGITAL S YSTEMS I Spring 20 10 S OLUTIONS OF P RACTICE P ROBLEMS — S ET 3 1. P ROBLEM 7.10 Assume that the reset signal is active high. In other words, if reset =1 then the counter goes to state 000010. 2. C OUNTER D ESIGN Design a counter that counts in the following sequence: 001, 010, 011, 100, 101, and repeat. Use JK flip-flops in your implementation. By using Karnaugh Maps or by inspection of the above table, we get the following equations: , , , , and . The counter schematic is thus as shown above. Clk Q 0 P T CLR LD QD QB QC QA D B C A RCO 163 Q 1 Q 2 Q 3 Q 5 Q 4 Clk P T CLR LD QD QB QC QA D B C A RCO 163 1 1 1 0 0 0 0 0 0 0 1 1 1 Q 5 Q 4 Q 0 Q 1 reset Current State Next State inputs of JK flip-flops Q 2 Q 1 Q 0 Q 2 + Q 1 + Q 0 + J 2 K 2 J 1 K 1 J 0 K 0 000xxxxxxxxx 0010100x1xx1 0100110xx01x 0111001xx1x1 100101x00x1x 101001x10xx0 110xxxxxxxxx 111xxxxxxxxx Q 1 Q 0 JK flip-flop JK flip-flop Clk J 0 K 0 J 1 K 1 Q 2 JK flip-flop J 2 K 2 1 Q 0 Q 1 Q 2 J 0 1 = J 1 K 0 Q 2 == K 1 Q 0 = J 2 Q 1 Q 0 = K
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This note was uploaded on 04/25/2011 for the course EEC 180A taught by Professor Redinbo during the Spring '08 term at UC Davis.

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SP10-pp3-sol - UNIVERSITY OF CALIFORNIADAVIS DEPARTMENT OF...

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