SP10-hw4 - (summarized in the table below) on the two data...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
UC Davis 1 Hussain Al-Asaad U NIVERSITY OF C ALIFORNIA —D AVIS D EPARTMENT OF E LECTRICAL OMPUTER E NGINEERING EEC180A — D IGITAL S YSTEMS I Spring 20 10 P ROBLEM S ET 4 Due Date: 9:00 AM, Thursday, May 1 3, 2008 1. Design a gate-level circuit that computes the function , where the input X is a 3- bit unsigned number represented by X 2 X 1 X 0 and the output Y is a 7-bit unsigned number represented by Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 . Minimize the number of gates in your design. (30 points) 2. Design a bit slice of the ALU shown below. The ALU performs one of the two operations
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: (summarized in the table below) on the two data inputs A = A n – 1 ...A and B = B n – 1 ...B according to the value of the logic/arithmetic mode input M. (40 points) 3. Show how to implement a JK flip-flop using an RS flip-flop and few logic gates. (30 points) Y 2 X 2 = C C 1 M C 2 M C n –1 M C n M A B A 1 B 1 A n – 1 B n – 1 F F 1 F n – 1 Slice 0 Slice 1 Slice n – 1 .... M ALU Operation F = A X OR B 1 F = A PLUS B...
View Full Document

This note was uploaded on 04/25/2011 for the course EEC 180A taught by Professor Redinbo during the Spring '08 term at UC Davis.

Ask a homework question - tutors are online