SP08-exam2-sol

# SP08-exam2-sol - UNIVERSITY OF CALIFORNIADAVIS DEPARTMENT...

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UC Davis 1 Hussain Al-Asaad U NIVERSITY OF C ALIFORNIA —D AVIS D EPARTMENT OF E LECTRICAL & C OMPUTER E NGINEERING EEC180A—D IGITAL S YSTEMS I S PRING 2008 E XAM II S TUDENT I NFORMATION I NSTRUCTIONS The exam is closed book and notes. A single double-sided cheat sheet is allowed. Print your name and your ID number. There are four problems in the exam. Solve all of them and show your work. If you need more space for your solution, use the back of the sheets. E XAM G RADE Name Hussain Al-Asaad ID Number xxx-xx-xxxx Problem Maximum Points Student Score 12 5 2 5 22 5 2 5 32 5 2 5 42 5 2 5 Total 100 100

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UC Davis 2 Hussain Al-Asaad 1. A RITHMETIC C IRCUITS (15 + 10 = 25 POINTS ) Let X be a 3-bit two’s complement number represented by X 2 X 1 X 0 and let Y be a 5-bit two’s complement number represented by Y 4 Y 3 Y 2 Y 1 Y 0 . 1.1 Design a gate-level circuit C that computes the function . Minimize the number of gates in your design. Assume that the input combination X 2 X 1 X 0 = 100 will never appear at the inputs of C . Moreover, you can assume that the literals and their complements are available. Method 1: Method 2: Multiplying by 2 is equivalent to shifting left the 2’s complement number representa- tion by one bit. For example, multiplying 3 (0011 in binary) by 2 yields 6 (0110 in binary) which is a shift of 1-bit to the left. Consequently, multiplying the number X 2 X 1 X 0 by 4 yields X 2 X 1 X 0 00. Adding three to the result yields X 2 X 1 X 0 11. Hence we can get Y 4 Y 3 Y 2 Y 1 Y 0 = X 2 X 1 X 0 11 which is the same result as Method 1. 1.2 Suppose that we have an 8-bit adder (shown below), show how we can implement the function .
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## This note was uploaded on 04/25/2011 for the course EEC 180A taught by Professor Redinbo during the Spring '08 term at UC Davis.

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SP08-exam2-sol - UNIVERSITY OF CALIFORNIADAVIS DEPARTMENT...

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