This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: load D Q C S S 1 I I 1 I 2 I 3 Y 4x1 Mux b Two-bit mode input: b 00 – no change b 01 – shift left b 10 – shift right b 11 – parallel load D Q C S S 1 I I 1 I 2 I 3 Y 4x1 Mux D Q C S S 1 I I 1 I 2 I 3 Y 4x1 Mux CMPT 150 Registers Page 5 Binary n-bit Counters b An n-bit binary counter has n FF’s that cycle through the sequence (for example): b Notice: b b L = b U = CMPT 150 Registers Page 6 One-bit Counter State Diagram: Excitation Table Curr Next State input State output L D U FF input D D i 0 0 1 1 1 1 CMPT 150 Registers Page 7 One-bit Counter D Q C b Logic diagram: b Using the 1-bit counter we’ve designed we can build a 3-bit counter as follows: L A U C 1-bit count L A U C 1-bit count L A U C 1-bit count...
View Full Document
This note was uploaded on 04/27/2011 for the course CMPT 150 taught by Professor Dr.anthonydixon during the Spring '08 term at Simon Fraser.
- Spring '08