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lecture21 - load D Q C S S 1 I I 1 I 2 I 3 Y 4x1 Mux b...

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CMPT 150 Registers Page 1 Registers box5 A register stores a multi-bit data word box5 Essentially it is a group of flip- flops box5 One flip-flop for each bit D Q C D Q C box5 On each clock rising/falling edge, value of I is captured and available as A box5 Problem: D Q C D Q C CMPT 150 Registers Page 2 Parallel-load Register box5 D flip-flop makes it tricky box5 Value is gone on next clock pulse box5 Solution: Add a load D Q C D Q S I 0 I 1 Y 2x1 Mux S Y input box5 If load is 0, A does not change box5 box5 If load is 1, A = I box5 C D Q C D Q C I 0 I 1 2x1 Mux S I 0 I 1 Y 2x1 Mux S I 0 I 1 Y 2x1 Mux CMPT 150 Registers Page 3 Shift Registers box5 A shift register is a register that can shift its value either left or right box5 E.g. Some uses for shift registers: box5 box5 Serialize data for transmission box5 Multiply or divide an integer by two box5 Simple unidirectional shift register: D Q C D Q C D Q C D Q C CMPT 150 Registers Page 4 Bidirectional Shift Register box5 A more useful shift register is a bidirectional shift register with parallel load D Q C S 0 S 1 I 0 I 1 I 2 I
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Unformatted text preview: load D Q C S S 1 I I 1 I 2 I 3 Y 4x1 Mux b Two-bit mode input: b 00 – no change b 01 – shift left b 10 – shift right b 11 – parallel load D Q C S S 1 I I 1 I 2 I 3 Y 4x1 Mux D Q C S S 1 I I 1 I 2 I 3 Y 4x1 Mux CMPT 150 Registers Page 5 Binary n-bit Counters b An n-bit binary counter has n FF’s that cycle through the sequence (for example): b Notice: b b L = b U = CMPT 150 Registers Page 6 One-bit Counter State Diagram: Excitation Table Curr Next State input State output L D U FF input D D i 0 0 1 1 1 1 CMPT 150 Registers Page 7 One-bit Counter D Q C b Logic diagram: b Using the 1-bit counter we’ve designed we can build a 3-bit counter as follows: L A U C 1-bit count L A U C 1-bit count L A U C 1-bit count...
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