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HW1 Solutions
1.
In 1995, the IBM AS/400 line of computers transitioned from a CISC instruction set to a
RISC instruction set. Due to the simpler instruction set, the realizable clock frequency for a
given technology generation and the CPI metric improved dramatically. However, for the
same reason, the number of instructions per program also increased noticeably. Given the
following parameters, compute the total performance improvement that occurred with this
transition. Furthermore, compute the breakeven clock frequency, breakeven cycles per
instruction, and breakeven code expansion ratios for this transition, assuming the other two
factors are held constant.
Total performance improvement:
TPP
IMPI
= 1000 IPP x 7 CPI x 1/50MHz = 140us
TPP
PowerPC
= 3300 IPP x 2.8 CPI x 1/150MHz = 61.6us
Speedup = 140/61.6 = 2.27 or 127%
Frequency breakeven: 7000/50 = 9240/50y => y = 9240/7000 = 1.32
CPI breakeven: 7000/50 = 23100y/150 => y = 21000/23100 = 0.91
IPP breakeven: 7000/50 = 2800y/150 => y = 21000/2800 = 7.5
Therefore, gaining 32% in frequency, or reducing CPI by 9%, or increasing pathlength by no
more than 7.5x (all in isolation) would all have provided constant performance across the
IMPItoPowerPC transition.
2.
A program’s run time is determined by the product of instructions per program, cycles per
instruction, and clock frequency. Assume the following instruction mix for a MIPSlike
RISC instruction set: 15% stores, 25% loads, 15% branches, and 30% integer arithmetic, 5%
integer shift, and 5% integer multiply. Given that stores require one cycle, load instructions
require two cycles, branches require four cycles, integer ALU instructions require one cycle,
and integer multiplies require ten cycles, compute the overall CPI.
Performance Factor
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 Spring '10
 DR.RAHULA

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